基于可配置异步反馈环形振荡器的真随机数发生器

作为现代加密系统不可或缺的一部分,真随机数发生器(TRNG)在信息安全中具有非常重要的作用。 本文提出了一种 可配置、轻量级、高吞吐量的真随机数发生器。 该结构利用与非门和异或门构成了可配置的异步反馈环形振荡器,通过在短时 间内增加相位噪声,来扩大时间抖动范围,从而改善了熵源的随机性。 该结构在 Xilinx Kintex-7 进行了多次测试验证,实验结果 表明,在不同温度(0℃ ~ 80℃ )和不同输出电压(0. 8~ 1. 2 V)的环境变化下,所提出的 TRNG 具有较强的鲁棒性,在硬件资源上 仅消耗了 43 个 LUTs 和 6 个 DFFs,并且获得高达 300 Mb / s 的吞吐量。 同时,生成的随机比特流能够以较高的 P 值通过 NIST SP800-22 和 NIST SP800-90B 测试。     

一种高吞吐率自治布尔网络真随机数发生器

真随机数发生器在硬件与信息安全领域具有广泛的应用前景。为提高真随机数发生器的吞吐率与降低硬件开销，以相互耦合的基本逻辑单元构成自治布尔网络做熵源，利用一阶高频振荡环增强网络刷新频率和多级非线性放大，从而获得高熵值混沌信号，结合DFF和XOR组成的后处理电路，设计构成真随机数发生器并在FPGA平台上实现。通过数据的采样和实时提取，然后对数据执行NIST SP800-22和SP800-90B随机性测试，并对其偏移度、自相关性及最大李雅普诺夫指数等性能进行评估。结果表明，真随机数发生器能够以600 Mbit/s的吞吐率产生熵值0.994 847 bit/sample的随机数序列，而且具有低的偏移度和自相关性及较低的硬件开销。     

基于LabVIEW的真随机数云发生器的设计

云发生器是构造云模型不确定性推理和设计云模型智能控制器的基础,全面论述了一种基于硬件真随机数云发生器的实现方法.首先设计一种基于雪崩噪声电路产生的真随机数序列发生器,利用LabVIEW平台构建测试系统对其进行一系列特性检验,进而将该真随机数序列转换为正态分布的真随机数作为云发生器的随机数源,最后设计一种真随机数云发生器算法,并通过LabVIEW平台编程实现.实验结果表明,该真随机数云发生器生成结果十分理想,可为云模型不确定性推理后续研究提供基础.     

基于FPGA的高速伪随机序列发生器设计

随着现代通信系统处理的最大数据速率的不断提高,需要高速的伪随机测试信号发生器。通过对m序列生成原理的研究,提出了一种基于FPGA的高速伪随机序列产生的方法。该方法基于m序列的采样定理和移位相加性,并行产生多组初始相位不同的m序列,最后通过模2加法器获得高速的m序列。从m序列的基本原理出发,给出了实现该高速m序列发生器的硬件设计,并用ModelSim软件对其进行仿真。实验结果表明,使用该方法实现的伪随机序列发生器,结构简单、速度快。     

基于并串转换的多通道高速伪随机序列发生器

研制了一款通用的多通道高速伪随机序列发生器.该发生器基于FPGA利用并串转换和时钟树技术实现,包含4个并行的通道,跳变速率智能可调,且伪随机序列有多种选择,可以为m序列、伯努利序列等等.同时对高速信号进行了信号完整性仿真,经测试,设计的高速伪随机序列发生器生成的伪随机序列波形和仿真结果相吻合,正负取值的幅度误差小于100 bmV,最小脉冲宽度为0.5 ns,跳变速率可达2 Gbps.该伪随机序列发生器可作为混频信号用于调制宽带转换器系统中,也可用于通信、雷达、超声波测距等领域.     

基于振动信号的锂离子电池故障诊断方法

为实现对锂离子电池过充及外部短路故障的诊断,提出一种基于改进变分模态分解(VMD)-多尺度熵(MSE)的锂离子电池振动信号特征提取方法.通过改进VMD对振动信号进行分解,对所得固有模态分量求多尺度熵值,提取锂离子电池在不同工况下的振动特征,最后基于此特征进行K均值聚类,完成对过充和外部短路故障的故障识别.经对比实验验证,该方法能有效提取锂离子电池振动信号特征量,正确识别锂离子电池的过充及外部短路故障,且准确率更优.     

基于混合半云模型的风速-功率曲线建模方法

风速-功率曲线的准确建模是风电机组出力态势评估和风电功率预测的关键基础之一。计及风电映射关系的不确定性及功率曲线的分布形态,提出一种基于混合半云模型的建模策略来实现对风功率数据固有和随机分布特征的挖掘和建模。引入最优组内云熵算法快速有效地剔除异常数据;采用逆向云发生器求取期望、熵与超熵数字特征来定量刻画风速-功率对应关系的不确定性,构建腰部数据的半云模型;通过X条件云发生器和正向云发生器分别求取腰部和上部数据的功率云滴,实现定性数字特征向定量数据的转换。以中国东北某大型风电场的实测数据为例,从数据质量、频率分布和风功率预测等维度分析混合半云模型,验证了所提方法的可行性。     

基于XILINX-FPGA的信号发生器实验设计

在Xilinx公司的EXCD-1开发平台上,基于MicroBlaze软核的嵌入式处理器系统,应用FPGA嵌入式技术开发出信号发生器实验。该实验通过外部输入信号周期、信号类型等信息,由开发板输出相应频率的波形离散值,再通过D/A和发大器得到相应频率的模拟信号。该实验可分为不同的难度等级,可适合于不同学习水平的学生要求。同时采用逐渐深入的设计形式,有利于培养学生的兴趣和提高学生的实践能力。     

局部放电趋势分析方法初步研究

在综合研究局部放电的各种统计特征参数的基础上,将金融时序分析方法引入局部放电,提取了一种基于平均放电量与放电次数的综合特征参数——放电量放电次数趋势(PVT),相比其它的特征参数,PVT能够更清晰地显示局部放电的发展趋势并揭示出变化过程中存在的异常现象。文中通过两个具体的应用实例,对PVT参数的性能进行了验证,初步的研究结果表明,PVT能为局部放电的严重程度评估提供有效的支持。     

基于虚拟仪器的电力线信道噪声发生器的设计

为了方便对中压电力线通信调制与编码硬件电路的调试,提出一种基于虚拟仪器技术的中压电力线信道噪声发生器的设计方法,利用该方法设计的噪声发生器可模拟产生电力线信道的背景噪声、随机突发噪声等。本设计利用MATLAB建立符合中压电力线信道噪声特性的噪声模型,以此模型为基础,通过MATLAB与LabVIEW混合编程,基于虚拟仪器采集卡输出参数可变的噪声,并通过功放电路输出。实验结果表明,该噪声发生器能够产生符合信道噪声特性的噪声信号,可以为实验室测试调制与编码硬件电路的性能提供便利。     

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.     

Chaotic cellular neural network‐based true random number generator

This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd.     

Truly random number generators based on non‐autonomous continuous‐time chaos

A novel non‐autonomous continuous‐time chaotic oscillator suitable for high‐frequency integrated circuit realization is presented. Simulation and experimental results, verifying the circuit feasibility, are given. Two methods for using this oscillator as the core of a random number generator are also proposed. Numerical binary data obtained according to the proposed methods pass the four basic tests of FIPS‐140‐2, while experimental data pass the full NIST‐800‐22 random number test suite. Copyright © 2008 John Wiley & Sons, Ltd.     

Hardware implementation of a strong pseudorandom number generator based block-cipher system for color image encryption and decryption

This paper proposed a hardware architecture of a strong block-cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high-level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S-box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA-Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works.     

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.     

Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis

This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)?intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits.     

于改进抽样法的电力系统可靠性评估

由于电力系统的元件故障为小概率事件,在应用传统非序贯蒙特卡洛抽样法进行系统可靠性评估时,存在抽样次数大,仿真时间长等缺点。通过将对偶变数抽样法与交叉熵重要抽样法相结合,提出了一种适用于电力系统可靠性评估的改进抽样方法。该方法首先通过交叉熵重要抽样确定元件最优参数,构造元件的零方差概率密度函数的近似函数,然后根据最优参数进行对偶抽样,进一步降低抽样过程的方差,提高了传统蒙特卡洛法的抽样效率。应用该方法及传统随机抽样法、对偶变数抽样法和交叉熵重要抽样法对IEEE-RTS（可靠性校验系统）与变参数后的IEEE-RTS进行可靠性评估,计算结果表明：提出的方法在保证一定计算精度的条件下,相比其他方法,进一步提高了仿真速度。越是小概率事件,方法的优势越明显。     

Design tradeoff analysis of floating-point adders in FPGAs

With gate counts of ten million, field-programmable gate arrays (FPGAs) are becoming suitable for floating-point computations. Addition is the most complex operation in a floating-point unit and can cause major delay while requiring a significant area. Over the years, the VLSI community has developed many floating-point adder algorithms aimed primarily at reducing the overall latency. An efficient design of the floating-point adder offers major area and performance improvements for FPGAs. Given recent advances in FPGA architecture and area density, latency has become the main focus in attempts to improve performance. This paper studies the implementation of standard; leading-one predictor (LOP); and far and close datapath (2-path) floating-point addition algorithms in FPGAs. Each algorithm has complex sub-operations which contribute significantly to the overall latency of the design. Each of the sub-operations is researched for different implementations and is then synthesized onto a Xilinx Virtex-II Pro FPGA device. Standard and LOP algorithms are also pipelined into five stages and compared with the Xilinx IP. According to the results, the standard algorithm is the best implementation with respect to area, but has a large overall latency of 27.059 ns while occupying 541 slices. The LOP algorithm reduces latency by 6.5% at the cost of a 38% increase in area compared to the standard algorithm. The 2-path implementation shows a 19% reduction in latency with an added expense of 88% in area compared to the standard algorithm. The five-stage standard pipeline implementation shows a 6.4% improvement in clock speed compared to the Xilinx IP with a 23% smaller area requirement. The five-stage pipelined LOP implementation shows a 22% improvement in clock speed compared to the Xilinx IP at a cost of 15% more area.     

微型计算机上的随机数发生器

蒙特卡洛方法在高电压技术中的应用日益广泛。为了在PC机上实现蒙特卡洛方法,随机数发生器的构成是关键问题之一。研究了按位求余的方法可充分利用PC机的可用整数范围,得到了循环周期较长的伪随机数系列。研究的随机数发生器通过了分布检验和相关检验。使用结果表明,发生器的性能是满意的。