一种基于环形振荡器的轻量级高效率的真随机数发生器

真随机数发生器(TRNG)作为芯片中重要的安全组件,在现代加密系统中扮演着越来越重要的角色。对于TRNG的设计,关键是需要熵提取器可以在恶劣的环境变化(如工艺波动、电压和温度(PVT))下稳定地生成熵值。基于Xilinx FPGA平台提出了一种基于环形振荡器的低成本,高效率真随机数发生器。TRNG一方面通过快速进位逻辑来提高熵提取的效率,另一方面通过优化电路结构和延迟,在以相对较低的资源开销情况下实现可观的吞吐量和随机性。TRNG分别在多块Xilinx Virtex6 FPGAs和Xilinx Spartan6 FPGAs上进行验证,实验数据测试结果表明,所提出的TRNG能够在广泛的PVT范围内表现出良好的鲁棒性,且生成的随机比特流不仅以相当高P值通过NIST SP800-22统计测试套件,而且可以通过最新的NIST SP800-90B测试。     

基于可配置异步反馈环形振荡器的真随机数发生器

作为现代加密系统不可或缺的一部分,真随机数发生器(TRNG)在信息安全中具有非常重要的作用。 本文提出了一种 可配置、轻量级、高吞吐量的真随机数发生器。 该结构利用与非门和异或门构成了可配置的异步反馈环形振荡器,通过在短时 间内增加相位噪声,来扩大时间抖动范围,从而改善了熵源的随机性。 该结构在 Xilinx Kintex-7 进行了多次测试验证,实验结果 表明,在不同温度(0℃ ~ 80℃ )和不同输出电压(0. 8~ 1. 2 V)的环境变化下,所提出的 TRNG 具有较强的鲁棒性,在硬件资源上 仅消耗了 43 个 LUTs 和 6 个 DFFs,并且获得高达 300 Mb / s 的吞吐量。 同时,生成的随机比特流能够以较高的 P 值通过 NIST SP800-22 和 NIST SP800-90B 测试。     

基于LabVIEW的真随机数云发生器的设计

云发生器是构造云模型不确定性推理和设计云模型智能控制器的基础,全面论述了一种基于硬件真随机数云发生器的实现方法.首先设计一种基于雪崩噪声电路产生的真随机数序列发生器,利用LabVIEW平台构建测试系统对其进行一系列特性检验,进而将该真随机数序列转换为正态分布的真随机数作为云发生器的随机数源,最后设计一种真随机数云发生器算法,并通过LabVIEW平台编程实现.实验结果表明,该真随机数云发生器生成结果十分理想,可为云模型不确定性推理后续研究提供基础.     

片上三角波信号发生器实现方法

针对混合信号电路内建自测试(BIST)结构中信号发生器的设计问题,本文提出了一种基于码密度直方图法测量模-数转换器性能的片上模拟三角波信号发生器的实现方法。该信号发生器由两个恒流源、电容和反馈控制电路组成,其中恒流源采用自偏压的Widlar电流源实现。实验结果表明,该信号发生器所生成的三角波信号不仅斜波部分具有良好的性线,而且其频率和幅值均可调。另外,该信号发生器结构精简,硬件开销小,易于片上集成。     

WiNoC中基于Edge-first算法的流量平衡设计

在无线片上网络中,无线节点拥塞以及不同子网和全局网络内的流量平衡情况对整个片上网络的通信效率有着重要的影响,为此提出了基于Edge-first算法的全局流量平衡机制(GTB)。首先优化了划分有线无线数据包的机制,减少了无线节点处的拥塞;其次根据无线路由器(WR)的拥塞情况,提出Edge-first路由算法平衡子网内的流量;最后在全局网络中提出了全局子网拥塞感知(GSCA)判断机制,使得长距离数据包优先从低拥塞子网通过,平衡了全局网络的流量。实验表明,该方案在可接受的硬件开销、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并且大幅的提升了网络的流量平衡性能。     

WiNoC中基于Edge first算法的流量平衡设计

在无线片上网络中,无线节点拥塞以及不同子网和全局网络内的流量平衡情况对整个片上网络的通信效率有着重要的影响,为此提出了基于Edge first算法的全局流量平衡机制（GTB）。首先优化了划分有线无线数据包的机制,减少了无线节点处的拥塞;其次根据无线路由器（WR）的拥塞情况,提出Edge first路由算法平衡子网内的流量;最后在全局网络中提出了全局子网拥塞感知（GSCA）判断机制,使得长距离数据包优先从低拥塞子网通过,平衡了全局网络的流量。实验表明,该方案在可接受的硬件开销、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并且大幅的提升了网络的流量平衡性能。     

RFID多碰撞位联合锁位动态可调整算法研究

针对现有RFID多标签防碰撞算法无法兼顾减小传输开销与降低碰撞率的缺点,提出了一种基于多碰撞位联合锁位动态可调防碰撞算法的系统。系统工作流程包括空闲时隙检测和多标签动态识别,空闲时隙检测用于锁定空闲时隙,以避免阅读器访问增大时间开销;多标签识别采用动态可调整防碰撞算法,其由多碰撞位联合锁位防碰撞算法和动态二叉树算法构成,阅读器根据曼彻斯特译码结果检测碰撞,估算标签数量,从而调用不同的防碰撞算法,成功识别一个标签后返回到上一次发生碰撞的节点。仿真结果表明,通信速率125 Kbit/s条件下,系统在传输开销、寻呼指令开销、吞吐率性能方面有明显的提高。     

基于结构平衡理论的电网自组织临界态辨识

准确度量复杂电网自组织临界态对于电力系统连锁故障的预防控制以及电网的升级改造均具有重要的应用价值。该文将电网输电线路虚拟为节点,以输电线路间的相互关联作用为边,综合考虑线路初始负载率、负载率增量和负载率增量的平均值定义了输电线路间相互影响的符号属性,进而构建了以线路重要度为点权、以线路间相互影响的符号属性为边权的电力系统状态关联网络。借鉴一般符号网络的结构平衡理论,建立并分析了电力系统运行状态平衡结构的模式及分类。在此基础上,提出了电力网络不平衡度的综合评价指标,该指标既可表征线路间潮流分布特性,又可表征能量化系统的扰动化解能力,可用于度量系统的自组织临界态。仿真结果表明,网络不平衡度在不同网架结构、潮流熵和负荷水平下均能有效识别电网自组织临界态,特别是在低负荷、低潮流熵工况下,仍有较强的适应性。     

基于混合半云模型的风速-功率曲线建模方法

风速-功率曲线的准确建模是风电机组出力态势评估和风电功率预测的关键基础之一。计及风电映射关系的不确定性及功率曲线的分布形态,提出一种基于混合半云模型的建模策略来实现对风功率数据固有和随机分布特征的挖掘和建模。引入最优组内云熵算法快速有效地剔除异常数据;采用逆向云发生器求取期望、熵与超熵数字特征来定量刻画风速-功率对应关系的不确定性,构建腰部数据的半云模型;通过X条件云发生器和正向云发生器分别求取腰部和上部数据的功率云滴,实现定性数字特征向定量数据的转换。以中国东北某大型风电场的实测数据为例,从数据质量、频率分布和风功率预测等维度分析混合半云模型,验证了所提方法的可行性。     

基于无线网络的智能节点设计

数据链路层引入仲裁机制,报文可以按照优先级先后发送而不会冲突,实现了多主网络。应用层引入对象建模,对象编址,基于连接的思想和生产者/消费者网络模型,提高了系统的开放性和网络吞吐率。     

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.     

Hardware implementation of a strong pseudorandom number generator based block-cipher system for color image encryption and decryption

This paper proposed a hardware architecture of a strong block-cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high-level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S-box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA-Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works.     

Chaotic cellular neural network‐based true random number generator

This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd.     

基于流量的自适应退避算法

通过对SMAC协议仿真分析,得到节点队列长度与网络流量以及占空比［3］之间的关系,并对此关系进行理论分析,在理论验证的基础上,针对SMAC协议固定竞争窗口的缺陷提出了一种基于流量的自适应退避算法,根据流量变化改变竞争窗口的大小,从而缓解网络流量高时激烈的信道竞争,减小网络流量低时空闲侦听时间,信道利用率显著提高。并通过NS2.35［10］仿真平台进行验证分析,结果表明在网络延迟、能耗和吞吐量等方面优于采用随机退避机制的SMAC协议［5］。     

基于“包-电路”交换的双环片上网络设计

针对包交换片上网络(NoC)在大量数据通信情况下性能较差的弱点,提出了一种基于“包-电路”(PCC)交换的环形拓扑结构片上网络(DRNoC)设计架构。首先这种双环形拓扑结构由内外两环构成,可实现环内或环间双向通信,环上节点数目可拓展。其次DRNoC路由器通道可配置为桥节点或环节点路由器两种类型,相比于2D-Mesh型通道数减少,结构更加简单,资源消耗更少。最后提出了针对DRNoC的双环动态路由算法(DDRA),该算法无需在每个路由节点都进行输出方向的译码判断,在头包建立受阻时,根据网络情况选择其他路由路径,最大程度保证数据同环传输基础上跨环传输,有降低头包建立的等待时间,提高吞吐率。实验表明,在大量数据通信情况下,搭载DDRA算法的DRNoC的硬件资源开销降低的同时能够降低网络平均包延时提升平均吞吐率,有效地改善了网络性能。     

Truly random number generators based on non‐autonomous continuous‐time chaos

A novel non‐autonomous continuous‐time chaotic oscillator suitable for high‐frequency integrated circuit realization is presented. Simulation and experimental results, verifying the circuit feasibility, are given. Two methods for using this oscillator as the core of a random number generator are also proposed. Numerical binary data obtained according to the proposed methods pass the four basic tests of FIPS‐140‐2, while experimental data pass the full NIST‐800‐22 random number test suite. Copyright © 2008 John Wiley & Sons, Ltd.     

First direct implementation of a true random source on programmable hardware

True random sources are not implementable in digital hardware, so that many practical applications have historically relied on pseudo‐random generators in order to avoid the potentially long prototyping times and the costs of dedicated analog design. However, pseudo‐random sources have liabilities that make them hardly suitable for some tasks (notably security related ones). Previous attempts to conciliate security, cost‐effectiveness, and rapid development included the exploitation of the analog accessory parts often present on programmable devices. In these designs some analog blocks are used for their side effects (noise amplification) rather than for their originally intended behaviour. Conversely, here we report a direct implementation of a true random source on programmable, low‐cost, general‐purpose hardware, where all blocks are used only for their nominal function. To the best of the authors' knowledge, this is the first proposal of this sort. The design exploits an FPAA, and is based on a non‐linear system exhibiting chaotic behaviour. Measures confirm the correct operation, high throughput, and robustness of the system. Copyright © 2005 John Wiley & Sons, Ltd.     

自适应二进制算术编码的动态可重构实现研究

针对H.266/VVC视频编码标准下的上下文自适应二进制算术编码器编码速度慢、资源开销大的问题,面向可重构结构依据算法的内在并行特性优化了编码架构,并基于动态可重构阵列处理器设计实现了CABAC编码器常规编码模式下的并行映射方法,阵列结构能够根据编码输入对优化后的算法进行动态重构,在避免专用硬件编码器较高的资源开销情况下利用软件重构的方法实现熵编码过程,保证编码准确性的同时提高了视频数据流编码效率,为此类运算密集型算法的硬件实现提供了更为灵活高效的参考途径。仿真结果表明,映射实现的编码过程中每个编码周期完成5个二进制序列的编码,平均编码效率达到384.13Mbin/s。基于FPGA的测试结果表明,软件重构方法与专用硬件实现的编码器相比,资源开销降低且编码效率提升5.47%,与同类型可重构视频编码结构相比,编码效率提升7.03%。     

A high‐speed MIMO FFT processor with full hardware utilization

The conventional way to design multi‐input‐multi‐output (MIMO) fast Fourier transform (FFT) processors for MIMO‐orthogonal frequency division multiplexing systems is to adopt a parallel architecture which uses as many single‐input‐single‐output FFT processors as the number of transmit/receive antennas. These MIMO FFT processors can provide high throughput, but they perform with low hardware utilization when there are not all input sequences available. In this paper, we propose a high‐speed MIMO FFT processor which can work efficiently with high throughput and full hardware utilization for variable 1 to 4 input sequences. Our MIMO FFT processor is designed by reordering and distributing data sequences to all data paths and is constructed by some novel modules. Being synthesized by using UMC 0.18‐μm process demonstrates that our 64‐point 4 × 4 FFT can achieve high throughput with full hardware utilization and perform correctly up to 62.25 MHz with low power consumption for variable 1 to 4 input sequences.