A Novel Depletion-Mode MOS Gated Emitter Shorted Thyristor

More attention has been given to the MOS-gated thyristor and several device struc-tures of MOS-gated thyristor have been reported,such as MOS-controlled thyristor(MCT) [1 ] ,depletion-mode thyristor (DMT) [2 ] ,field assisted turn-off...     

SiC field-effect devices operating at high temperature

Field-effect devices based on SiC metal-oxide-semiconductor (MOS) structures are attractive for electronic and sensing applications above 250°C. The MOS device operation in chemically corrosive, high-temperature environments places stringent demands on the stability of the insulating dielectric and the constituent interfaces within the structure. The primary mode of oxide breakdown under these conditions is attributed to electron injection from the substrate. The reliability of n-type SiC MOS devices was investigated by monitoring the gate-leakage current as a function of temperature. We find current densities below 17 nA/cm² and 3 nA/cm² at electric field strengths up to 0.6 MV/cm and temperatures of 330°C and 180°C, respectively. These are promising results for high-temperature operation, because the optimum bias point for SiC MOS gas sensors in near midgap, where the field across the oxide is small. Our results are valid for n-type SiC MOS sensors in general and have been observed in both the 4H and 6H polytypes.     

A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.     

Short-channel MOSFET's in the punchthrough current mode

Results of two-dimensional device analysis are compared with experiment for 0.8-µm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power-law dependence of IDSversusV_{DS} (V_{GS} = V_{SB} = 0)is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program (SUPREM) and device-simulation program (CADDET), is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.     

Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1.5 V supply voltage, 20 MHz clock frequency, and less than 0.1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feed through errors from switches cancel out. The MOS current mode S/H circuit is designed and simulated using CMOS 0.6 m device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0.1%, and 1 MHz input from a 1.5 V power supply is achievable.     

A new MOS photon-counting sensor operating in the above-breakdown regime

A solid-state optical sensor based on a buried-channel charge-transfer MOS structure and operated at voltages in the above, breakdown regime is proposed. In this mode of operation the MOS photosensor performs as a photon counter with, it is suggested two significant advantages over similar sensors based on p-n junction diodes, namely: self-quenching of the avalanche discharge and possible implementation in the form of a self-scanned CCD array. In this first demonstration of the proposed device, discrete structures in silicon are investigated experimentally. It is demonstrated that internal gains of 3 × 10⁶electrons/photon are possible during operation at about 10 V above breakdown. It is also shown that, after accousting for dark generation and retriggering effects, the photon-induced count rate saturates with increasing bias above breakdown. The results are in excellent agreement with the theoretical predictions from a two-dimensional model and imply that, at 10-15 V above breakdown avalanche initiation probabilities for electrons in excess of 0.9 have been attained.     

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f/sub t//spl middot/L/sub g/ product of 12GHz/spl middot//spl mu/m at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f/sub t//spl middot/L/sub g/ product of 6GHz/spl middot//spl mu/m was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.     

A new semiconductor switching device

A new bipolar-type semiconductor switching device is proposed, fabricated by two diffusion processes and without any isolation technique. The device has an n⁺-diffused small electrode instead of a gate electrode in the MOS transistor structure. This device can have high photo sensitivity in the charge storage mode operation.     

High-density static ESFI MOS memory cells

The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 /spl mu/m/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells known so far. The static and dynamic behavior of these cells are discussed, as well as their behavior in a large-scale integrated (LSI) circuit; for this purpose an exploratory memory with 4096 bits and with simple decoding and sensing circuitry has been realized on an area of 3.5/spl times/4.2 mm (140/spl times/170 mils). Taking into account the measured data, an ESFI MOS memory circuit shows a better performance in speed and power dissipation than dynamic MOS memories, but its principal advantage is the static operation mode.     

A novel single gate MOS controlled current saturated thyristor

A novel single gate MOS controlled current saturation thyristor (MCST) device is proposed. In the on-state the MCST operates in thyristor-like mode at low anode voltage and enters the IGBT-like mode automatically with increasing anode voltage, offering a low on-state voltage drop and current saturation capability. Simulation results based on 6.5 kV trench devices indicate the turn-off energy loss of the MCST is reduced by over 35% compared to the IGBT. The saturation current density of the MCST is strongly dependent on the on-set voltage of the p ⁺ buffer/n-well junction, leading to its excellent safe operation area (SOA) and making it suitable for high power applications     

Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics.     

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.     

New two-terminal C-MNOS memory cells

New two-terminal nonvolatile memory cells are proposed, in which an n-channel MNOS transistor is functionally integrated with a p-channel MNOS or MOS transistor. The operational principle of both types of the cells is substantially based on the Λ (lambda)-shaped I-V Characteristic of complementary FET's. The most valuable feature of the new cells is the unipolar pulse operation of the simple diode-matrix array which can be used in a RAM mode by the use of selective writing and erasing as well as in an electrically alterable PROM mode.     

An effect of the subthreshold current on scaled-down MOS dynamic RAMs

Data-output holding characteristics of MOS dynamic RAMs with 2.5 /spl mu/m design rules are studied by employing the hidden-RAS-only-refresh mode. It is verified that the noise voltage caused by internal circuit operation increases the subthreshold current and that the clamp circuitry effectively decreases the subthreshold current.     

High-voltage double-implanted power MOSFET's in 6H-SiC

We report on the first planar high-voltage MOSFET's in 6H-SiC. A double-implant MOS (DIMOS) process is used. The planar structure ameliorates the high-field stressing encountered by SiC UMOS transistors fabricated by other groups. Blocking mode operation of up to 760 V is demonstrated, which is nearly three times higher than previously reported operating voltages for SiC MOSFET's     

Localized interface trap generation in SILO-isolated MOSFETs duringPECVD nitride passivation

The authors report the generation of interface traps during the plasma-enhanced chemical vapor deposition of silicon nitride passivation in MOS structures that utilize a sealed-interface local oxidation scheme (SILO) for device isolation. These traps are highly localized at the boundaries between gate and field oxides, causing enhanced subthreshold conduction. Localized interface traps of this type were not observed in identical MOS structures that use conventional LOCOS (local oxidation of silicon) isolation and were eliminated by thermal anneals at 450°C. Anneals in hydrogen ambients resulted in enhanced rates of hot-carrier-induced degradation. The high densities and localized nature of these anomalous traps make possible a novel mode of device operation in which source-drain conduction is strongly modulated by substrate bias     

High-frequency MOS digital capacitor

A MOS digital capacitor capable of operation at VHF and UHF frequencies is described. This new device is made up of a parallel combination of MOS capacitors each of which can be individually switched between two distinct capacitance values; a maximum binary state being the high-frequency MOS inversion capacity and the minimum being that of a deep-depletion MOS device, Switching is accomplished by on chip MOSFET's. Isolation of the RF terminals is accomplished by the high intervening channel impedances of the switching MOS gates. The basic structure and the principles of operation will be discussed, and operational performance figures for RF tuning range, linearity, dynamic range, and figure of merit Q will be presented.     

Analytical equations for oscillation amplitude of MOS Colpitts oscillator

New analytical equations are presented for amplitude analysis of metal–oxide–semiconductor (MOS) Colpitts oscillator. These equations are obtained from a large signal analysis that includes MOS operation in the saturation, triode and cutoff regions. The analysis is based on a reasonable estimation for the output voltage waveform. The estimated waveform must satisfy the nonlinear differential equations governing the circuit. The validity of the proposed method and the resulting equations has been verified through simulations using TSMC 0.18?µm complementary MOS process. The results are also compared with the other methods. Simulation results show high validity of the proposed equations.     

Sub-threshold leakage currents in weakly inverted short channel IGFETS

This paper attempts to develop a comprehensive device model suitable for computer aided design, in the sub-threshold mode of operation, for short-channel insulated-gate field-effect transistors (IGFETs). It is shown that, for state-of-the art MOS LSI, employing 4–6 μ channel length devices, the sub-threshold conduction current is influenced by the longitudinal electric field to a significant degree. The device model is found to be in close agreement with experimental data. The limitations of this model for very short channel IGFETs is briefly discussed.     

White noise in MOS transistors and resistors

The theoretical and experimental results for white noise in the low-power subthreshold region of operation of an MOS transistor are discussed. It is shown that the measurements are consistent with the theoretical predictions. Measurements of noise in photoreceptors-circuits containing a photodiode and an MOS transistor-that are consistent with theory are reported. The photoreceptor noise measurements illustrate the intimate connection of the equipartition theorem of statistical mechanics with noise calculations