Characterization of TiN/TiSi2 bilayer for application to ULSI

The properties of TiN/TiSi₂ bilayer formed by rapid thermal annealing (RTA) in an NH₃ ambient after the titanium film is deposited on the silicon substrate is investigated. It is found that the formation of TiN/TiSi₂ bilayer depends on the RTA temperature and a competitive reaction for the TiN/TiSi₂ bilayer occurs at 600°C. Both the TiN and TiSi₂ layers represent titanium-rich films at 600°C anneal. The TiN layer has a stable structure at 700°C anneal while the TiSi₂ layer has C₄₉ and C₅₄ phase. Both the TiN and TiSi₂ layers have stable structures and stoichiometries at 800°C anneal. When the TiN/TiSi₂ bilayer is formed, the redistribution of boron atoms within the TiSi₂ layer gets active as the anneal temperature is increased. According to secondary ion mass spectroscopy analysis, boron atoms pile up within the TiN layer and at the TiSi₂−Si interface. The electrical properties for n⁺ and p⁺ contacts are investigated. The n⁺ contact resistance increases slightly with increasing annealing temperature but the p⁺ contact resistance decreases. The leakage current indicates degradation of the contact at high annealing temperature for both n⁺ and p⁺ junctions.     

Novel Diffusion‐Barrier Materials Against Oxygen for High‐Density Dynamic Random Access Memory Capacitors

A new design concept for diffusion barriers in high‐density memory capacitors is suggested, and both RuTiN (RTN) and RuTiO (RTO) films are proposed as sacrificial oxygen diffusion barriers. The newly developed RTN and RTO barriers show a much lower sheet resistance than various other barriers, including binary and ternary nitrides (reported by others), up to 800 °C, without a large increase in the resistance. For both the Pt/RTN/TiSi_x/n⁺⁺poly‐plug/n⁺ channel layer/Si and the Pt/RTO/RTN/TiSi_x/n⁺⁺poly‐plug/n⁺ channel layer/Si contact structures, contact resistance—the most important electrical parameter for the diffusion barrier in the bottom electrode structure of capacitors—was found to be as low as 5 kohm, even after annealing up to 750 °C. When the RTN film was inserted as a glue layer between the bottom Pt electrode layer and the TiN barrier film in the chemical vapor deposited (Ba,Sr)TiO₃ (CVD–BST) simple stack‐type structure, the RTN glue layer was observed to be thermally stable to temperatures 150 °C higher than that to which the TiN glue layer is stable. Moreover, the capacitance of the physical vapor deposited (PVD)–BST simple stack‐type structure adopted TiN glue layer initially degraded after annealing at 500 °C, and, thereafter, completely failed. In the case of the RTN and RTO/RTN glue layers, however, the capacitance continuously increased up to 550 °C. Thus, the new RTN and RTO films, which act as diffusion barriers to oxygen, are very promising materials for achieving high‐density capacitors.     

Characterization of a rapid thermal anneal TiNxOy/TiSi2 contact barrier

In this paper, the physical and electrical properties of a TiN_xO_y/TiSi₂ dual layer contact barrier are reported. The TiN_xO_y/TiSi₂ barrier was formed by rapidly annealing a Ti thin film on Si in an N₂ ambient. During this process, the Ti film surface reacts with N₂ to form a TiN_xO_y skin layer and the bulk of the Ti film reacts with Si to form an underlying TiSi₂ layer. The influences of rapid thermal anneal (RTA) conditions on the TiN_xO_y layer were investigated by varying the RTA temperature from 600 to 1100° C and cycle duration from 30 to 100 s. It is found that the resulting TiN_xO_y and TiSi₂ layer thicknesses are dependent on RTA temperature and the starting Ti thickness. For a starting Ti thickness of 500Å, 150Å thick TiN_xO_y and 800Å thick TiSi₂ are obtained after an RTA at 900° C for 30 s. The TiN_xO_y thickness is limited by a fast diffusion of Si into Ti to form TiSi₂. When a Ti film is deposited on SiO₂, Ti starts to react with SiO₂ from 600° C and a significant reduction of the SiO₂ thickness is observed after an RTA at 900° C. The resulting layer is composed of a surface TiN_xO_y layer followed by a complex layer of titanium oxide and titanium suicide. In addition, when Ti is depos-ited on TiSi₂, thicker TiN_xO_y and TiSi₂ layers are obtained after RTA. This is because the TiSi₂ layer retards the diffusion of Si from the underlying substrate into the Ti layer. NMOSFETs were fabricated using the TiN_xO_y/TiSi₂ as a contact barrier formed by RTA at 900° C for 30 s and a significant reduction of contact resistance was obtained. In addition, electromigration test at a high current density indicated that a significant improvement in mean time to failure (MTF) has been obtained with the barrier.     

Low-temperature CVD TiN as a diffusion barrier between gold and silicon

Low-temperature (200°C), atmospheric pressure chemical vapor deposited (APCVD) titanium nitride films are shown to be effective diffusion barriers for the Au/TiN/Si contact scheme. The samples were analyzed by Rutherford backscattering spectroscopy (RBS), and by optical microscopy. It was found that a pure TiN layer constitutes an effective barrier for 40 min at 550°C, at which point the TiN cracks and peels. Even thin layers of TiN (200Å thick) can significantly reduce the amount of interdiffusion between the gold and silicon.     

Amorphous Ta-nanocrystalline RuOx diffusion barrier for lower electrode of high density memory devices

The effects of the amount of RuO₂ added in the Ta film on the electrical properties of a Ta-RuO₂ diffusion barrier were investigated using n⁺⁺-poly-Si substrate at a temperature range of 650–800°C. For the Ta layer prepared without RuO₂ addition, Ta₂O₅ phase formed after annealing at 650°C by reaction between Ta and external oxygen, leading to a higher total resistance and a non-linear I-V curve. Meanwhile, in the case of the Ta film being deposited with RuO₂ incorporation, not only a lower total resistance and ohmic characteristics exhibited, but also the bottom electrode structure was retained up to 800°C, attributing to the formation of a conductive RuO₂ crystalline phase in the barrier film by reaction with the indiffused oxygen because of a Ta amorphous structure formed by chemially strong Ta-O or Ta-Ru-O bonds and a large amount of conductive RuO₂ added. Since a kinetic barrier for nucleation in formation of the crystalline Ta₂O₅ phase from an amorphous Ta(O) phase is much higher than that of crystalline RuO₂ phase from nanocrystalline RuO_x phase, the formation of the RuO₂ phase by reaction between the indiffused oxygen and the RuO_x nanocrystallites is kinetically more favorable than that of Ta₂O₅ phase.     

Finite metal-sheet-resistance in contact resistivity measurements: Application to Si/TiN contacts

The standard transmission line model cannot be applied to evaluate the contact resistivity of thin TiN layers on highly doped p⁺ and n⁺ substrates because the finite sheet resistance of the TiN must be accounted for. We present two ways to include this effect using existing analytical models. The results are shown to agree with measurements where the effect of the finite sheet resistance of TiN is eliminated with a metallic overlayer. With the help of these evaluation techniques, it is shown that the contact resistivity of TiN changes in opposite ways for p⁺ and n⁺Si after vacuum annealing at 600°C for 15 min. This result is consistent with an increase of the barrier height φ_Bn of the contact by ?0.1 V to near midgap value.     

Formation mechanism of InxGa1−xAs ohmic contacts to n-type GaAs prepared by radio frequency sputtering

The formation mechanisms of InAs/Ni/W ohmic contacts to n-type GaAs prepared by radio-frequency (rf) sputtering were studied by measuring contact resistances (R_c) using a transmission line method and by analyzing the interfacial structure mainly by x-ray diffraction and transmission electron microscopy. Current-voltage characteristics of the InAs/Ni/W contacts after annealing at temperatures above 600°C showed “ohmic-like behavior.” In order to obtain the “ohmic” behavior in the contacts, pre-heating at 300°C prior to high temperature annealing was found to be essential. The contacts showed ohmic behavior after annealing at temperatures in the range of 500∼850°C and contact resistance values of as low as ∼0.3Ω-mm were obtained. By analyzing the interfacial structures of these contacts, In_xGa_1−xAs layers with low density of misfit dislocations at the In_xGa_1−xAs and GaAs interface were observed to grow epitaxially on the GaAs substrate upon heating at high temperatures. This intermediate In_xGa_1−xAs layer is believed to divide the high energy barrier at the contact metal and GaAs interface into two low barriers, resulting in reduction of the contact resistance. In addition, Ni was found to play a key role to relax a strain in the In_xGa_1−xAs layer (introduced due to lattice mismatch between the In_xGa_1−xAs and GaAs) by forming an intermediate Ni_xGaAs layer on the GaAs surface prior to formation of the In_xGa_1−xxAs layer.     

Characterization of sputtered Ta-C-N film in the Cu/barrier/Si contact system

Characterization of sputtered tantalum carbon nitride (Ta-C-N) film in Cu/barrier/Si system was reported for the first time. With a 50∶50 wt.% TaC target and an optimum N₂/Ar flow rate (in sccm) ratio of 2/24, a 600 Å-thick sputtered Ta-C-N layer was shown metallurgically stable up to 650°C annealing for 30 min, which is about 100°C higher as compared to the case without nitrogen doping. Cu diffusion through the local defects or grain boundaries of the Ta-C-N barrier layer into Si substrate is the dominant factor responsible for the failure of the Ta-C-N barrier layer after high temperature annealing.     

CdTe solar cell in a novel configuration

Polycrystalline thin‐film CdTe/CdS solar cells have been developed in a configuration in which a transparent conducting layer of indium tin oxide (ITO) has been used for the first time as a back electrical contact on p‐CdTe. Solar cells of 7·9% efficiency were developed on SnO_x:F‐coated glass substrates with a low‐temperature (<450°C) high‐vacuum evaporation method. After the CdCl₂ annealing treatment of the CdTe/CdS stack, a bromine methanol solution was used for etching the CdTe surface prior to the ITO deposition. The unique features of this solar cell with both front and back contacts being transparent and conducting are that the cell can be illuminated from either or both sides simultaneously like a ‘bi‐facial’ cell, and it can be used in tandem solar cells. The solar cells with transparent conducting oxide back contact show long‐term stable performance under accelerated test conditions. Copyright © 2004 John Wiley & Sons, Ltd.     

Interfacial reactions and electrical properties of Hf/p-Si0.85Ge0.15

Interfacial reactions and electrical properties of Hf/p-Si_0.85Ge_0.15 as a function of the annealing temperature were studied. Hf₃(Si_1−xGe)₂ and Hf(Si_1−xGe)₂ were initially formed at 500°C and 600°C, respectively. At temperatures above 400°C, Ge segregation out of the reacted layers associated with strain relaxation of the unreacted Si_0.85Ge_0.15 films appeared. At 780°C, agglomeration occurred in the Hf(Si_1−xGe_x)₂ films. All the as-deposited and annealed Hf/p-Si_0.85Ge_0.15 samples showed the formation of an ohmic contact. The lowest specific contact resistance around 10⁻⁵ ω cm² could be obtained for the Hf₃ (Si_1−xGe_x)₂ contacts to p-Si_0.85Ge_0.15 formed at 500°C. Below 500°C, the decrease of specific contact resistance with the annealing temperature is mainly caused by the formation of Hf₃(Si_1−xGe_x)₂ and an interfacial Ge-rich layer between the Hf₃(Si_1−xGe_x)₂ and unreacted Si_0.85Ge_0.15 films, while above 600°C, the increase of specific contact resistance may be due to the formation of Hf(Si_1−xGe_x)₂ and SiC as well as the roughness of the Hf(Si_1−xGe_x)₂ films.     

Low-temperature processing of shallow junctions using epitaxial and polycrystalline CoSi2

Cobalt disilicide is grown epitaxially on (100) Si from a 15 nm Co/2 nm Ti bilayer by rapid thermal annealing (RTA) at 900°C. Polycrystalline CoSi₂ is grown on (100) Si using a 15 nm Co layer and the same annealing condition. Silicide/p⁺-Si/n-Si diodes are made using the silicide as dopant source:¹¹B⁺ ions are implanted at 3.5–7.5 kV and activated by RTA at 600–900°C. Shallow junctions with total junction depth (silicide plus p⁺ region) measured by high-resolution secondaryion mass spectroscopy of 100 nm are fabricated. Areal leakage current densities of 13 nA/cm² and 2 nA/cm² at a reverse bias of -5V are obtained for the epitaxial silicide and polycrystalline silicide junctions, respectively, after 700°C post-implant annealing.     

Electrical properties of Ru and RuO2 gate electrodes for Si-PMOSFET with ZrO2 and Zr-silicate dielectrics

In this work, we have studied the electrical and thermal stability of Ru and RuO₂ electrodes on ZrO₂ and Zr-silicate dielectrics. Very low resistivity Ru and rutile stoichiometric RuO₂ films, deposited by reactive sputtering, were evaluated as gate electrodes on ultrathin ZrO₂ and Zr-silicate (∼2.7 nm) films for Si-PMOS devices. Thermal and chemical stability of the electrodes were studied at annealing temperatures up to 800°C in N₂ followed by a forming gas anneal. X-ray diffraction (XRD), transmission electron microscopy (TEM), and x-ray photoelectron spectroscopy (XPS) methods were used to study grain structure and interface reactions. Electrical properties were evaluated using MOS capacitors. The role of oxygen in these dielectrics was studied by comparing equivalent oxide thickness (EOT) changes as a function of annealing temperature for capacitors with ZrO₂ and Zr-silicate dielectrics. For capacitors with Ru and RuO₂ gate electrodes on both ZrO₂ and Zr-silicate, excellent stability of EOT was detected. Flatband voltage and gate current as a function of annealing temperature were also studied. These studies indicate that Ru and RuO₂ are promising gate electrodes for P-MOSFETs.     

Fifteen-Nanometer Ru Diffusion Barrier on NiSi/Si for a sub-45 nm Cu Contact Plug

A ruthenium film on a NiSi/Si substrate was evaluated for barrier performance in Cu contact metallization. The films were deposited by magnetron sputtering using Ni, Ru, and Cu targets. The low-resistivity NiSi film was initially produced from an Ni/Si substrate, and Ru and Cu films were sequentially deposited on the NiSi/Si substrate so that barrier performance could be studied. Barrier properties were elucidated by four-point probe measurement, x-ray diffractometry, scanning electron microscopy, Auger electron spectroscopy, and transmission electron microscopy. The stability temperatures of 600°C (Cu/NiSi/Si) and 650°C (Cu/Ru/NiSi/Si) were systematically verified and are discussed. Structural analysis indicated that the failure mechanism involved penetration of the Cu through the Ru/NiSi stacked film at a specific temperature, which induced the accelerated dissociation of the NiSi. Interposition of an Ru layer between the Cu and the NiSi/Si effectively prevented intermixing and substantially improved the thermal stability in the Cu/NiSi/Si stack films.     

Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory

The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO₂‐Al₂O₃‐ZrO₂/TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO₃, which has a dielectric constant of >100, even at a thickness ～10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO₂ and Al‐doped TiO₂ films might find space to fill the gap between ZAZ and SrTiO₃ MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO₂‐based dielectrics, which depends on having a dense, uniform and smooth RuO₂ layer as bottom electrode. Although the Ru (and RuO₂) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO₄ precursor made a thin, uniform, and denser Ru and RuO₂ layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO₃ films, grown at 370 °C, was ～150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO₃ film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.     

Nickel silicide formation on Si(100) and Poly-Si with a presilicide N2 + implantation

The key feature of this study is to incorporate N₂ ⁺ implant prior to Ni sputtering on the poly-Si gate and source/drain regions. The results show that the incorporation of the presilicide N₂ ⁺ implant is able to suppress agglomeration in the Ni silicide films up to 900°C and enhance the phase stability of NiSi on Si(100) up to 750°C. Stable and low sheet resistance was achieved on the silicided undoped poly-Si up to 700°C due to reduced layer inversion, which is driven by grain boundary energy and the surface energy of the poly-Si.     

Cd and Te-based ohmic contact materials to p-Type ZnSe

In order to explore a possibility of forming an intermediate semiconductor layer with low Schottky barrier by the conventional deposition and annealing technique, the electrical properties of Cd and Te-based contacts on the nitrogendoped ZnSe substrates have been investigated. Cd in the Cd/W contact reacted with the ZnSe substrate after annealing at temperatures above 250°C and formed epitaxial Cc_x}Zn_1−xSe layers, leading to reduction of the “turn-on” voltage (V_T) from about 11 to 6 V (here, a slash “/” between Cd and W means the deposition sequence). The reduction of the V_n} value by annealing at elevated temperatures was also observed for the Bi-Cd/W and In-Cd/W contacts. The average Cd composition (x) in the Cd_n}Zn_1−xSe layers was measured to be larger than 0.9, which agreed with the values estimated from the calculated Cd-Zn-Se phase diagrams. The ohmic behavior was strongly influenced by the thickness of the Cd_xZn_1−xSe layer, the density of misfit dislocations formed at the interface between the Cd_x Zn_1−x Se and the ZnSe, and/or the total area of the Cd Zn. Se layers covering the ZnSe surface. The present result suggests that formation of the large-areal Cc_xZn_1−xSe layers with thin thickness is crucial to achieve further reduction of the V_T value by the conventional deposition and annealing technique. Also, the V_T reduction was not obtained for the Te/W contact even after annealing at temperatures close to 300°C, which was explained to be due to absence of ternary ZnSe_1−xTe_n intermediate layers.     

Band-edge metal gate materials for atomic-layer-deposited HfO2 for future CMOS technology

In this paper, two different materials are studied for silicon band edge work function. Sc metal gate with thin interface TaN_x layer is investigated for n-channel metal-oxide semiconductor (NMOS) metal gate application. The control of TaN_x layer thickness is necessary to achieve improved thermal stability and work function (WF) as low as 4.0 electron volts (eV). RuO_x also has been demonstrated for p-channel metal-oxide semiconductor (PMOS) application. RuO_x WF tends to increase in comparison with elemental Ru metal. This may be due to improved thin film properties like better adhesion and roughness for RuO_x. Overall both Sc and RuO_x are revealed as candidate materials for future CMOS technology.     

InxGa1−xAs ohmic contacts to n-type GaAs with a tungsten nitride barrier

Significant reduction of the contact resistance of In_0.7Ga_0.3As/Ni/W contacts (which were previously developed by sputtering in our laboratory) was achieved by depositing a W₂N barrier layer between the Ni layer and W layer. The In_0.7Ga_0.3 As/Ni/W₂N/W contact prepared by the radio-frequency sputtering technique showed the lowest contact resistance of 0.2 Ωmm after annealing at 550°C for 10 s. This contact also provided a smooth surface, good reproducibility, and excellent thermal stability at 400°C. The polycrystalline W₂N layer was found to suppress the In diffusion to the contact surface, leading to improvement of the surface morphology and an increase in the total area of the In_xGa−As between metal and the GaAs substrate. These improvements are believed to reduce the contact resistance.     

InxGa1-xAs ohmic contacts to n-type GaAs prepared by sputter deposition

Thermally stable, low contact resistance InAs/Ni/W contacts were previously prepared by sputter depositing InAs, Ni, and W targets in our laboratory. However, the optimum annealing temperature to provide low contact resistance (R_c) was high, resulting in rough contact surface. In the present experiment, the effects of the In concentrations of In_xGa_1-x As targets on the optimum annealing temperature to prepare low R_cand the surface morphology of the_xGa_1-x/ W contacts were studied. In addition, the electrical properties and the interfacial microstructure were correlated to search the optimum In concentration to provide the minimum R_c, where the interfacial microstructure was analyzed by x-ray diffraction and transmission electron microscopy and the contact resistances (R_cc) were measured by the transmission line method. The optimum annealing temperature to provide minimum R_c was reduced by 150°C by using the In_0.7Ga_0.3As targets instead of the previous targets. The contact resistance of 0.4 Ω-mm was obtained for the In_0.7Ga_0.3As/Ni/W contacts after annealing at temperatures of around 600°C. The R_c values did not deteriorate after annealing at 400°C for 2 h. Also, the surface of this contact was smooth and no evidence of In outdiffusion on the contact surface was seen. Finally, the effect of the In concentrations at the metal/GaAs interfaces on the electrical properties will be discussed.     

Microstructure of reactively sputtered oxide diffusion barriers

Molybdenum oxide (Mo_1-x O _x ) and ruthenium oxide (RuO₂) films were prepared by rf reactive sputtering of Mo or Ru targets in an O₂/Ar plasma. Both films exhibit metallic conductivities. The influence of the deposition parameters on the phase that forms and on the microstructure of Mo_1-x O _x and RuO₂ films is reported. A phase transformation is observed in Mo_1-x O _x films subjected to heat treatment. The diffusion barrier performance of Mo_1-x O _x and RuO₂ layers interposed between Al and Si is compared.