一种基于频差法的顺序等效采样方法及其实现

基于频差法原理实现顺序等效采样方法,将时域问题转化到频域进行处理,理论上分析其可行性,给出频率差值的计算方法,可以通过频差设计任意等效采样频率.经过电路板实验验证,该方法简化了步进延时系统的复杂度,降低延时路径上的引入的干扰,目前实现的最小步进延时为1.71ps,最高顺序等效采样率约为585GS/s.为了缩短基于频差法的顺序等效采样所需的总时间,提出了倍频采样时钟的技术.该方法可以扩展应用到许多等效采样的领域中.     

Pulse and time-domain measurements

A review of the state of the art and science of pulse parameter measurements is given including recent advances in the use of real-time oscilloscopes, waveform recorders, equivalent time sampling oscilloscopes, and counter timers in the measurement of repetitive and single transient signals. Recent advances in the use of artifact waveform standards and modern signal analysis techniques to compensate for measurement distortion are highlighted. The formation and progress of an IEEE committee which is developing a performance standard for waveform recorders is also described.     

基于千兆网的高帧频视频采集系统

高帧频视频图像采集是测试技术领域的重要组成部分,系统根据B码时统的高精度信号,由控制计算机通过软件修正摄像机曝光信号时间,实现了高帧频视频图像和测控数据的同步采集,设计了一种无信息损失的高帧频(1 000 F/s)、高分辨率视频图像和测控数据同步采集系统。利用千兆以太网把图像数据从相机的FLASH内无失真转储到计算机硬盘内,并在转储过程中把同步测量数据合成到对应的图像帧频上。     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique

This paper presents a circuit technique for the design of a wideband on-chip sampling oscilloscope in mixed-signal integrated circuits. A coupled Phase Locked Loop (PLL) and Delay Locked Loop (DLL) module is designed to generate a high-resolution sampling clock over a limited time interval. This module has been employed as an enabling circuit to support on-chip measurement of fast waveforms through a subsampling technique attaining less than 10 ps sampling resolution. Input waveforms are first divided into equal-size-segments in the time domain and then each segment is subsampled with the sampling clock supplied by the coupled PLL and DLL module. The proposed measurement scheme has been fabricated in CMOS 0.18 μm technology and the measurement results indicate that over 7 effective bits of measurement linearity can be achieved for input signals up to 1.6 GHz.     

分数倍延时数字滤波器设计

在时分交替ADC结构中,由于各子通道ADC采样时钟的偏差,导致通道采样信号误差,严重影响时分交替ADC的动态性能.针对时分交替ADC中子通道的时钟偏差,在信号精确重构的理论依据下,采用基函数分段拟合和频域逼近的方式设计延时低通滤波器.通过改变基函数的定义域,推导了[-Ts,0]内误差校正的理论基础,并结合基函数设计和频...     

光电经纬仪动态误差修正方法

针对光电经纬仪红外相机测量系统动态测量精度低的问题,提出了一种通过修正各分系统之间延时时间从而提高动态测量精度的方法。首先介绍了光电经纬仪红外相机测量系统的组成和测量原理,分析了大地坐标系下物像空间的对应关系,指出了影响光电经纬仪红外相机测量系统的原因是相机内方位元素的准确性和光学畸变校正效果。分析了影响光电经纬仪红外相机测量系统动态测量精度的原因,提出了采用各分系统根据工作参数采用不同延时时间的误差修正方法。实验结果验证了该方法的正确性和准确性,标定结果与精度比对实验结果表明,经过动态测角修正的方位角与高低角测角误差均方根值分别由27.89与17.67提高到10.07与8.56,该方法有效地提高了动态测量精度,并且对其他光电测量设备具有参考价值。     

Fiber-optic reflection measurements using OCWR and OTDR techniques

A method for determining the backscatter and reflection responses of an optical fiber and reflector to an arbitrary input is developed. Two cases are specifically considered: a continuous-wave input and a rectangular pulse input. From the rectangular pulse input response, the equation is derived for computing the reflectance of a discrete component from an optical time-domain reflectometer (OTDR) measurement. Precautions are given for accurately performing reflectance measurements using an OTDR. Two methods are presented for determining the backscatter level of the fiber type under test, and its importance in reflection measurements is shown     

A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation

A continuous-time system that converts its analog input to a continuous-time digital representation without sampling, then processes the information digitally without the aid of a clock, is presented. Without sampling there is no aliasing, which reduces the in-band distortion power by not aliasing into band out-of-band distortion components. The 8-bit system, fabricated in a 90 nm CMOS process, utilizes continuous delay elements as part of a programmable transversal FIR filter. The input is encoded by a delta modulator without a clock into a series of non-uniformly spaced tokens, which are processed by the digital continuous-time filter and converted to an analog output using a custom DAC that guarantees there are no glitches in the output waveform. All activity is signal driven, automatically affording dynamic power scaling that tracks input activity.      

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters： State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.     

Single-Chip Adaptive Transversal Filter IC Employing Switched Capacitor Technology

Development of compact, high-speed, and low power adaptive transversal filters (ATF's) has been of great interest. Such ATF's have already been successfully fabricated in monolithic form employing a short channel MOSFET process and switched capacitor technique, using only complete analog circuit technology while eliminating inherent analog problems. This IC with five taps works with both ±5 V and 10 V supplies at a clock rate of more than 250 kHz. It has been designed for multipurpose applications such as a decision feedback equalizer (DFE), echo canceller (EC), and linear equalizer (LE), the last of which has already been reported [5]. The architecture to realize these applications will be described first. Much discussion is presented on the investigation of the operation, characteristics, and performance limitations of this IC in the DFE mode, from which those in the EC mode for two-wire full-duplex data transmission can be understood. For a single echo with magnitude of one half that of the original signal and delay time of one clock period from the original signal, and convergence factor of 0.2 for weight adaptation, the DFE operating at the clock rate of 100 kHz completes equalization within about 1.2 ms resulting in a residual rms distortion of -45.4 dB. The dominant performance limitation factors are found to be both the correlator harmonic distortion and transversal filter noise, but not the convolver harmonic distortion which is the dominant factor for the LE.     

基于FPGA的数字存储示波器

数字示波器由程控放大电路、采样保持电路、高速数据采集、示波显示调理4个模块组成。系统以FPGA（现场可编程门阵列）为控制核心,FPGA内嵌RAM存储波形数据,终端采用X、Y轴方式显示,低频段实现了10^6次采样／s实时采样,高频段实现了200MHz等效采样,等效采样时钟由FPGA内置锁相环时钟分频得到,分频算法经优化具有极高的精度,被测波形频谱覆盖了20Hz～10MHz,波形显示无明显失真。     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

A 4-GHz effective sample rate integrated test core for analog andmixed-signal circuits

An area-efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). Several prototypes were fabricated in a triple-metal 3.3-V 0.35-μm CMOS process, and were demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks at a clock rate of 20 MHz (limited by our experimental setup). Designed for 8 bits of quantization, a spurious-free dynamic range (SFDR) of 65 dB at 500 KHz and 61 dB at Nyquist (20.001 MHz) was demonstrated using our prototypes. High-frequency narrow-band signals (extending into the gigahertz range) have been captured through subsampling and the use of a high-bandwidth front-end sampling network. Similarly, circuit phenomena that are broadband in nature were measured by using a delayed-clock subsampling mechanism in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. Delaying the clock is performed using a voltage-controlled delay line tuned by a self-biased delay-locked loop, which allowed for a timing resolution of about one gate delay (~200 ps). The proposed test core occupies an area equivalent to only about 7000 standard-cell 2-input NAND gates     

基于菲涅耳反射的准分布式光纤温度传感器

基于菲涅耳反射原理和光时域反射(OTDR)技术,提出了一种新型的、结构简单的准分布式光纤温度传感器.传感器由两个端面抛光的光纤对接构成,并在两端面间隙中填充温敏材料.传感器周围温度变化改变温敏材料的折射率,从而引起菲涅耳反射强度的变化.将三个传感头串联,利用OTDR探测各传感器菲涅耳反射的微弱变化实现温度传感和传感器定位.在-30～80℃范围内,随着温度升高,该系统各个传感头的菲涅耳反射强度单调增大,且温度传感特性具有良好的重复性,同时具有极低的附加损耗.     

Word-Synchronous Optical Sampling of Periodically Repeated OTDM Data Words for True Waveform Visualization

An improved phase-locked loop (PLL) for versatile synchronization of a sampling pulse train to an optical data stream is presented. It enables optical sampling of the true waveform of repetitive high bit-rate optical time division multiplexed (OTDM) data words such as pseudorandom bit sequences. Visualization of the true waveform can reveal details, which cause systematic bit errors. Such errors cannot be inferred from eye diagrams and require word-synchronous sampling. The programmable direct-digital-synthesis circuit used in our novel PLL approach allows flexible adaption of virtually any problem-specific synchronization scenario, including those required for waveform sampling, for jitter measurements by slope detection, and for classical eye-diagrams. Phase comparison of the PLL is performed at 10-GHz OTDM base clock rate, leading to a residual synchronization jitter of less than 70 fs.     

基于线性规划的Internet端到端时延的估计

测量Internet端到端时延特征是研究Internet端到端分组行为的重要内容之一,它能够应用于QoS(Quality of Service),SLA(Service Level Agreement)的管理、拥塞控制算法研究等许多方面.常用的端到端时延测量方法大多依赖于GPS接收机或采用NTP协议来实现收发端时钟的同步,但由于GPS接收机价格较高不可能每台主机都能配备, NTP协议的精度不能满足要求。该文基于线性规划的方法估计收发时钟的频差、相对时钟偏差等参数,以获得端到端时延的估计。作者在几条不同的链路上进行了测试,结果表明该方法能有效消除收发时钟不同步的影响。     

Design of a high speed parallel encoder for convolutional codes

This paper presents the design of high speed parallel architectures for convolutional encoders and its implementation on FPGA devices. Convolutional codes are widely used in telecommunication applications to improve the data transmission reliability over noisy chanels.The architecture proposed here combines parallel and pipelining techniques. A purely parallel approach can increase the number of processed bits per clock cycle. Unfortunately, the critical path propagation delay increases with the parallelism level. Consequently, the operating clock frequency decreases which in turn can dramatically limit the benefit of parallelization. This drawback can be significantly reduced using pipelining techniques. As a result, the critical path depends no more on the parallelism level.The encoder architectures have been implemented on FPGA devices of the Altera Flex10KE family. Bit rates up to 6.61 Gbits/s have been achieved on 32-bit parallel implementations.     

基于两层流水线结构的FIR滤波器设计

本文提出了一种基于两层流水线体系结构的FIR滤波器的实现方案(2HPFIR).采用比输入采样频率快几倍的内部时钟频率,实现了乘加器件的高度复用,进而缩减了芯片面积.根据滤波器的抽头数目N和内部时钟快于采样频率的倍数M,在二层流水线结构的抽头链中,加入N/M-1个抽头把运算分成N/M个组.在流水线结构的组内形成M个阶段,组间形成N/M个阶段.随着抽头数量的增长,此结构很容易扩展,且不会增加关键路径的延时.此方法可以灵活应用到其它类似的专用滤波器设计中.     

Effects of trap levels in single-photon optical time-domainreflectometry: evaluation and correction

Single photon detectors used in optical time-domain reflectometry (OTDR) suffer from carrier trapping phenomena. It is shown that trapping effects can result in a severe OTDR trace distortion, and that accurate measurements of trap releases open the way to the correction of the OTDR data. A simple procedure for offline correction of the experimental traces is presented. Its applicability range is analyzed, using a Monte Carlo program which simulates the actual OTDR experiments. A great improvement of signal-to-noise ratio in single-photon OTDR is expected by exploiting the technique. Requirements for the electronics to be used for these measurements are discussed