Hydrogen “doped” thin film diamond field effect transistors for high power applications

Early predictions that diamond would be a suitable material for high performance, high power devices were not supported by the characteristics of diodes and field effect transistors (FETs) fabricated on boron doped (p-type) thin film material. In this paper commercially accessible polycrystalline thin film diamond has been turned p-type by the incorporation of near surface hydrogen; mobility values as high as 70 cm² V⁻¹ s⁻¹ have been measured for films with a carrier concentration of 5×10¹⁷ cm⁻³. Schottky diodes and metal–semiconductor FETs (MESFETs) have been fabricated using this approach which display unprecedented performance levels; diodes with a rectification ratio >10⁶, leakage currents <1 nA, no indication of reverse bias breakdown at 100 V and an ideality factor of 1.1 have been made. Simple MESFET structures that are capable of switching V_DS values of 100 V with low leakage and current saturation (pinch-off) characteristics have also been fabricated. Predictions based upon experiments performed on these devices suggest that optimised device structures will be capable of operation at power levels up to 20 W mm⁻¹, implying that thin film diamond may after all be an interesting material for power applications.     

Characterization of the Back Interface in Strained-Silicon-on-Insulator Channel and Enhancement of Electrical Properties by Heat Treatment

The electrical characteristics of thin strained-silicon-on-insulator (sSOI) wafers were evaluated, and the effects of annealing processes on the back interface states of sSOI wafers were analyzed by using the back-gated (BG) metal–oxide–semiconductor field-effect-transistor structure. The electrical characteristics of the BG MOSFET fabricated on sSOI wafers were superior to that of conventional SOI wafers. However, the rapid thermal annealing (RTA) process induced significant degradations by increasing the back interface states between the strained-Si thin channel and the buried oxide layer. On the other hand, the conventional furnace annealing process at 500 $^{circ}hbox{C}$ in a nitrogen $(hbox{N}_{2})$ ambient was effective for reducing the RTA-induced back interface states, and the performances of the BG sSOI MOSFET annealed in $hbox{N}_{2}$ ambient were significantly improved.      

Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction

Measurements were performed in thin film silicon on insulator (SOI) nMOSFETs and it was observed a transition region in the subthreshold slope, larger than the theoretically expected, when the back interface (silicon film/buried oxide) changes from accumulation to depletion. Also, it was observed a non-constant plateau in the subthreshold slope when the back interface is accumulated.

MEDICI numerical bidimensional simulations were performed in order to analyze this transition region. It was verified that there is a back gate voltage range where a part of the back interface is not depleted over the whole subthreshold region, depending on the front gate voltage, which influences strongly the determination of the subthreshold slope, resulting in a non-abrupt transient region.

It is proposed a method for extracting the interface trap density in gate oxide/silicon film and silicon film/buried oxide interfaces minimizing the influence of the back accumulation layer in the subthreshold slope with the back interface accumulated. This method was also applied experimentally.     

Electrical characteristics of the interface between laser-recrystallized polycrystalline silicon and the underlying insulator

The effects of fabrication processes on the electrical characteristics of the interface between a thin laser-recrystallized polysilicon film and the underlying oxide insulator in a silicon-on-insulator (SOI) structure have been investigated. It has been found that an underlying oxide layer thermally grown in an oxygen and HC1 ambient resulted in the lowest fixed-oxide charge density. A double-layered 6 nm LPCVD nitride and a 10 nm plasma CVD oxide encapsulating structure deposited on the polysilicon film prior to laser recrystallization was also found to be effective in reducing the charge at the back interface. Oxide charge densities as low as 3 × 10¹¹cm^-2have been obtained, compared to the otherwise typical values of 1 to 2 × 10¹²cm^-2.     

A novel subthreshold slope technique for the extraction of theburied-oxide interface trap density in the fully depleted SOIMOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress     

SIMS study of silicon oxynitride prepared by oxidation of silicon-rich silicon nitride layer

We proposed a novel process for fabrication silicon oxide–oxynitride–oxide structure for ULSI device applications. By deposition of silicon-rich silicon nitride and then following a thermal oxidation process, a good oxynitride layer was obtained. Secondary ion mass spectroscopy (SIMS) study reveals that the hydrogen content of nitride film at the interface can be reduced by more than 40% when compared to stoichiometric nitride. With this method, high nitrogen content oxynitride and smoother oxynitride/oxide interfaces result in the reduction of the interface charge trapping remarkably.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

GaAs field effect transistors fabricated by imprint lithography

A GaAs metal–semiconductor field-effect transistor (MESFET) has been realized based on mix-and-match fabrication using optical lithography for the ohmic contacts and imprint lithography for the gate. The gate length and width are 1.2 and 80 μm, respectively, the channel length is 4 μm. For the gate definition a Si-mold is embossed into a thin polymer film located on top of an n-doped GaAs layer. The gate is fabricated by metal evaporation and lift-off.     

Thin RF sputtered and thermal Ta2O5 on Si for high density DRAM application

Tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O₂ mixture and thermal oxidation of tantalum layer on Si) have been investigated with respect to their dielectric, structural and electric properties. It has been found that the formation of ultra thin SiO₂ film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements, have indicated. The initial films (as-deposited and as-grown) are not perfect and contain suboxides of tantalum and silicon which act as electrical active centers in the form of oxide charges and interface states. Conditions which guarantee obtaining high quality tantalum oxide with dielectric constant of 32–37 and leakage current density less than 10⁻⁷ A/cm² at 1.5 V applied voltage (Ta₂O₅ thickness equivalent to about 3.5 nm of SiO₂) have been established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAM application.     

Schottky–ohmic transition in nickel silicide/SiC-4H system: is it really a solved problem?

The transition from Schottky to ohmic contact in the nickel silicide/SiC system during annealing from 600 to 950 °C was investigated by measuring the electrical properties of the contact and by analyzing the microstructure of the silicide/SiC interface. The graphite clusters formed by carbon atoms during silicidation are uniformly distributed into the silicide layer after annealing at 600 °C and they agglomerate into a thin layer far from the silicide/SiC interface after annealing at 950 °C. At this temperature an increase of the Schottky barrier height was measured, while deep level transient spectroscopy evidences the absence of the 0.5 eV peak related to the carbon vacancies.     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

Modeling the silicon–hafnia interface

We report first-principles calculations of the structure and electronic properties of several different silicon–hafnia interfaces. The structures have been obtained by growing HfO_x layers of different stoichiometry on Si(1 0 0) and by repeated annealing of the system using molecular dynamics. The interfaces are characterised via their electronic and geometric properties. Moreover, electronic transport through the interfaces has been calculated using finite-element-based Green's function methods. We find that oxygen always diffuses towards the interface to form a silicon dioxide layer. This results in the formation of dangling Hf bonds in the oxide, saturated by either Hf diffusion or formation of Hf–Si bonds. The generally poor performance of the interfaces suggests that it is important to stabilise the system with respect to oxygen lattice diffusion.     

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

Electroless deposition of novel Ag–W thin films

The seedless electroless deposition of silver–tungsten (Ag–W) thin films on silicon dioxide substrate was performed using wet palladium activation from ammonia–acetate and benzoate solutions. Introducing tungsten in the plating bath catalyzes the deposition for benzoic acid solution and decreases the deposition rate for ammonia–acetate solution. The tungsten content in the deposit was 0–1.0 at%, mainly in WO_x form. It was found that the electrical, optical, and mechanical properties of the Ag–W films depends on the W content in the deposit. The optimal Ag–W thin films that were deposited from either the ammonia–acetate or benzoate bath demonstrate good adhesion to the substrate, high brightness, and do not corrode at temperatures up to 350 °C in air. Sub-100 nm thick Ag–W deposits have demonstrated resistivity of about 4 μΩ cm after vacuum annealing at 350 °C for 1 h. Finally, we present the film microstructure characterization and discuss the possibility of using Ag–W thin films for advanced microelectronics metallization.     

Electrical and interface properties of Au/DNA/n-Si organic-on-inorganic structures

The effect of the thickness and coverage rate of a DNA film on the electrical and interface properties of Au/DNA/n-Si organic-on-inorganic structures has been investigated. The thin film properties of the DNA deposited on n-Si wafer were characterized by atomic force microscopy. The effect of the thickness and coverage rate of the DNA layer was investigated by evaluating electrical parameters, such as the barrier height, ideality factor, series resistance, and interface state density. The thickness and coverage rate of the DNA layer significantly affects the electrical properties of the Au/DNA/n-Si organic-on-inorganic structures. The interface state density properties of the Au/DNA/n-Si diodes were determined by conductance technique. The results show that the interface state density decreases with decrease in both film thickness and coverage rate of the DNA in an acetate buffer, modifying the electronic parameters of the Au/DNA/n-Si diodes.     

Structure-Induced Stability in Sinuous Black Silicon for Enhanced Hydrogen Evolution Reaction Performance

Clean energy infrastructures of the future depend on efficient, low-cost, long-lasting systems for the conversion and storage of solar energy. This is currently limited by the durability and economic viability of today's solar energy systems. These limitations arise from a variety of technical challenges; primarily, a need remains for the development of stable solar absorber–catalyst interfaces and improved understanding of their mechanisms. Although thin film oxides formed via atomic layer deposition have been widely employed between the solar absorber–catalyst interfaces to improve the stability of photoelectrochemical devices, few stabilization strategies have focused on improving the intrinsic durability of the semiconductor. Here, a sinuous black silicon photocathode (s-bSi) with intrinsically improved stability owing to the twisted nanostructure is demonstrated. Unlike columnar black silicon with rapidly decaying photocurrent density, s-bSi shows profound stability in strong acid, neutral, and harsh alkaline conditions during a 24-h electrolysis. Furthermore, scanning transmission electron microscopy studies prior to and post electrolysis demonstrate limited silicon oxide growth inside the walls of s-bSi. To the authors’ knowledge, this is the first time structure-induced stability has been reported for enhancing the stability of a photoelectrode/catalyst interface for solar energy conversion.     

High 366/254-nm Rejection Contrast GaN MIS Photodetectors Using Nano Spin-Oxide

In this paper, GaN-based metal–insulator–semiconductor (MIS) photodetectors (PDs) with liquid-phase deposition oxide (LPD oxide) or nanospin oxide were fabricated and compared. Compared to the MIS-PDs with LPD oxide, the nanospin-oxide device can dramatically reduce the optical response of 254 nm by two orders while still retaining the same 366-nm optical response as LPD oxide. The 366/254-nm rejection contrast is raised from 5.13 to 413 for the MIS-PDs with LPD and spin oxides, respectively. Thus, one can simply insert a thin (10 nm) nanospin-oxide layer between the metal and GaN to significantly reduce the response of 254 nm. Possible mechanism is discussed here.      

Study of GaN growth on ultra-thin Si membranes

10 μm-thick ultra-thin Si (1 1 1) membranes for GaN epi-layers growth were successfully fabricated on silicon-on-insulator (SOI) substrate by backside etching the handle Si and buried oxide (BOX) layer. Then 1 μm-thick GaN layers were deposited on these Si membranes by metal–organic chemical vapor deposition (MOCVD). The crack-free areas of 250 μm × 250 μm were obtained on the GaN layers due to the reduction of thermal stress by using these ultra-thin Si membranes, which was further confirmed by the photoluminescence (PL) spectra and the simulation results from the finite element method calculation by using the software of ANSYS. In this paper, a newly developed approach was demonstrated to utilize micromechanical structures for GaN growth, which would improve the material quality of the epi-layers and facilitate GaN-based micro electro-mechanical system (MEMS) fabrication, especially the pressure sensor, in the future applications.     

Focussed ion beam and field emission gun–scanning electron microscopy for the investigation of voiding and interface phenomena in thin‐film solar cells

The use of focussed ion beam milling combined with high resolution scanning electron microscopy analysis as a characterisation tool for thin‐film photovoltaics is reported. CdTe solar cell cross sections are examined in high detail with as‐grown and CdCl₂‐treated devices being compared. Observed changes in microstructure of the thin‐film layers are related to the device performance. The CdCl₂ treatment is shown to cause a reduction in the CdTe defect density at regions close to the interface and induce recrystallization of the CdS layer. Furthermore, the focussed ion beam technique is shown to reveal voids formed within the device's thin‐film layers at various processing stages that have not been previously observed in working cell structures. The back‐contacting Te‐rich layer resulting from nitric–phosphoric acid etching is also observed, with the etched layer being seen to propagate down the CdTe grain boundaries. Copyright © 2011 John Wiley & Sons, Ltd.