栅长对SOI NMOS器件ESD特性的影响

采用TLP测试的方式,研究了不同栅长对栅接地SOI NMOS器件ESD(Electrostatic discharge,静电放电)特性的影响,结果发现栅长越大,维持电压VH越大,ESD二次击穿电流It2越大;其原因可能与薄硅层中的热分布有关。     

一种内嵌NMOS的抗闩锁双向MHVDDSCR

针对双向可控硅(DDSCR)易发生闩锁效应的问题,提出了一种多路高维持电压DDSCR(MHVDDSCR)。在器件的两边嵌入NMOS管,构成电流通路,抽取阱内的空穴与电子,促使反偏PN结内电场增强,提高了维持电压。采用Sentaurus TCAD进行了仿真验证。结果表明,相比于传统LT_DDSCR,MHVDDSCR的触发电压降低了0.61 V,维持电压从2.10 V提高到7.13 V。该器件适用于狭窄ESD设计窗口的模拟IC的双向静电防护。     

用于ESD防护的PDSOI NMOS器件高温特性

研究了基于0.18μm部分耗尽型绝缘体上硅(PDSOI)工艺的静电放电(ESD)防护NMOS器件的高温特性。借助传输线脉冲(TLP)测试系统对该ESD防护器件在30~195℃内的ESD防护特性进行了测试。讨论了温度对ESD特征参数的影响,发现随着温度升高,该ESD防护器件的一次击穿电压和维持电压均降低约11%,失效电流也降低近9.1%,并通过对器件体电阻、源-体结开启电压、沟道电流、寄生双极结型晶体管(BJT)的增益以及电流热效应的分析,解释了ESD特征参数发生上述变化的原因。研究结果为应用于高温电路的ESD防护器件的设计与开发提供了有效参考。     

雪崩光电探测器的击穿效应模型分析

基于CMOS工艺制备了空穴触发的Si基雪崩探测器(APD),基于不同工作温度下器件的击穿特性,建立空穴触发的雪崩器件的击穿效应模型。根据雪崩击穿模型和击穿电压测试结果,拟合曲线得到击穿电场与温度的关系参数(dE/dT),器件在250～320 K区间内,击穿电压与温度是正温度系数,器件发生雪崩击穿为主,dV/dT=23.3 mV/K,其值是由倍增区宽度以及载流子碰撞电离系数决定的。在50～140 K工作温度下,击穿电压是负温度系数,器件发生隧道击穿,dV/dT=-58.2 mV/K,其值主要受雪崩区电场的空间延伸和峰值电场两方面因素的影响。     

一种用于5 V电源ESD防护的双MOS触发SCR

低电压触发的可控硅器件LVTSCR具有低触发特性,被广泛应用于静电放电(ESD)防护领域。为了避免LVTSCR在工作时发生闩锁效应和潜在失效,基于0.18 μm BCD工艺,提出一种双MOS触发的DMTSCR。TCAD仿真结果显示,相比传统LVTSCR,DMTSCR具有更低的触发电压和更高的维持电压,显著提高了器件的闩锁免疫力,同时消除了传统LVTSCR的潜在失效风险。该器件适用于5 V电源的ESD防护。     

基于传统的CMOS工艺延伸漏极NMOS功率管研究

延伸漏极N型MOS（EDNMOS）是基于传统低成本CMOS工艺设计制造，用N-well作为NMOS漏极漂移区，以提高其击穿电压。用二维器件模拟软件Medicici对该器件进行模拟分析，结果表明有效地提高了NMOS管击穿电压。实验结果表明采用这种结构能使低压CMOS工艺输出功率管耐压提高到电源电压的2．5倍，样管在5V栅压下输出的电流可达到750mA。作为开关管工作，对于1000pF容性负载，其工作电流在550mA时，工作频率可达500KHz。     

TLP应力下gg-NMOS瞬态特性分析

采用TCAD Sentaurus模拟分析了gg-NMOS在TLP应力下的瞬态特性.包括NMOS的栅长,栅氧化层厚度,栅宽及TLP电流大小对ESD保护器件开启特性的影响.分析表明,器件栅长增加,栅氧变厚,栅宽变宽都使得漏端过冲电压增大,达到这一电压所需时间变长.对于相同上升时间的TLP脉冲,大电流则对应短的上升时间和高的过冲电压.该工作为以后高响应速度ESD保护器件设计提供依据和参考.     

TVS二极管标称参数与静电放电防护能力研究

通过搭建ESD测试系统,测量TVS二极管的ESD防护性能,比较其标称参数与ESD防护性能之间的关系。结果表明,TVS二极管的反向击穿电压在一定程度上能够反映ESD防护能力,反向击穿电压与ESD峰值电流、ESD钳位电压呈线性关系,标称钳位电压略低于实际ESD钳位电压,而其他标称参数与ESD防护能力关联较小。标称参数难以全面反映器件的ESD防护能力。     

系统级测试下静电防护器件的失效机理分析

为满足系统级电磁兼容测试标准IEC61000-4-2,许多航空电子设备中都有静电放电(ESD)防护器件,其功能的失效直接影响到被保护电路和整机的安全性.在分析该类器件的失效机理时考虑到典型性,选择双极性ESD防护器件0603ESDA-TR作为受试对象,研究了系统级ESD注入对器件性能的影响,并对器件内部温度分布进行了仿真分析.研究表明ESD脉冲注入时雪崩电流在整个pn结面分布不均匀,仅集中在边缘几个点上,局部过热点的温度甚至达到硅熔融温度,将破坏原有的晶格结构,导致器件二次击穿而发生硬损伤.当ESD电压达到25 kV后,器件的性能参数开始退化,但反向漏电流几乎不变;连续100次脉冲后器件完全失效.分析后得出的结论是:ESD防护器件遭受系统级静电放电冲击时具有累积效应,其失效是由性能退化引起的,并且传统的漏电流检测无法探测到ESD引起的损伤.     

应用于5 V电压电路的新型闩锁免疫LVTSCR

传统低压触发可控硅(LVTSCR)维持电压过低,应用于片上ESD防护时存在闩锁风险。文章提出了一种嵌入分流路径的LVTSCR。基于0.18 μm CMOS工艺,使用Sentaurus-TCAD软件模拟人体模型,对器件准静态特性进行了分析。结果表明,新型器件在保持触发电压、ESD防护性良好的情况下,有效提高了维持电压。对关键尺寸D6进行优化,该器件的维持电压提高到5.5 V以上,器件可安全应用于5 V电压电路,避免了闩锁效应。     

Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage,Low Leakage Current,and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-togate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.     

静电放电作用下微波双极型晶体管的失效机理研究

通过理论建模和试验测试的方法研究了多指结构微波双极型晶体管在静电放电作用下的热稳定性和电稳定性。选择2SC3356作为受试器件,对100个测试样本进行人体模型静电放电注入实验,并从器件内部电场强度、电流密度和温度分布变化出发,用二维器件级仿真软件辅助分析了在静电放电应力下其内在损伤过程与机理。由于指间热耦合的存在,雪崩电流在各指上分布不均,局部的电流拥挤和过热效应会导致晶格损伤。试验结果表明,由于特殊的物理结构,受试器件对静电放电最敏感的端对并不是EB结,而是CB结,当静电放电电压增大到1.3KV时,CB结首先损坏。失效分析进一步表明静电放电引起的失效机理通常是介质层的击穿和局部铝硅共晶体的过热融化。静电放电注入实验的过程中存在积累效应,多次低强度的注入测试会导致潜在性失效并使器件性能大幅下降。     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。     

Investigation of a SiGe HBT during ESD stress in a 0.18-/spl mu/m SiGe BiCMOS process

This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-/spl mu/m SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process.