共查询到17条相似文献,搜索用时 291 毫秒
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循环冗余码(CRC)是USB协议中重要的错误检测措施。在此分析了USB3.0数据包的基本格式以及USB3.0协议中CRC校验的特点,针对USB3.0数据高速传输的要求,设计实现并行发送端CRC产生和接收端CRC校验电路,功能仿真结果证明了其有效性。 相似文献
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Unfolding算法实现的高速并行CRC电路的VLSI设计 总被引:1,自引:1,他引:0
文章通过分析Unfolding算法和被广泛应用的串行CRC校验电路,提出了一种新的高速并行CRC电路,给出了推导过程,并对它的优缺点进行了讨论。 相似文献
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针对任意位的CRC并行化方法及编解码器的实现 总被引:1,自引:0,他引:1
介绍了一种基于查表法的针对任意位数据的任意位CRC并行计算的原理及算法,克服了现有的两类CRC并行算法延时大、毛刺多或仅适于2^n位数据的2^n位CRC校验的缺点。该方法使并行CRC校验的传输数据位数与CRC码位数之间的选择更灵活,并且在加速比、功耗和面积等方面具有优势。 相似文献
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针对UHF RFID系统中的并行循环冗余校验电路进行了设计和详细的分析。首先对基于经典的线性反馈移位寄存器的串行CRC电路进行了介绍,然后在串行CRC电路的基础上采用迭代法推导出了8位并行CRC电路。UHF RFID系统中采用了CRC-16的校验方法,因此该文着重以CRC-16为例,用Verilog HDL硬件描述语言设计实现了8位并行CRC-16电路,利用ALTERA公司的仿真工具Modelsim对其进行了功能仿真,最后在Quartus II 11.0开发环境下烧录到FPGA芯片上进行了板级验证。结果符合设计的初衷:一次处理1个字节的数据,且满足UHF系统通信速率的要求。 相似文献
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提出了一种新的超高频射频识别(RFID)标签芯片的数据编解码与循环冗余校验(CRC)计算同步进行的电路结构。该电路采用ISO/IEC 18000.6C标准协议,在数据编解码过程中同步进行串行CRC计算来提高系统数据的处理速度。采用FPGA进行仿真分析。结果表明,该设计方法可实现CRC编解码与RFID数据的编解码同步,即不占用额外的时钟处理CRC计算,从而满足超高频RFID的快速通信要求。所提出的串行CRC电路在SIMC 0.18 μm标准CMOS工艺下进行综合,其面积比并行CRC电路节省31.4%,电路算法更简单。 相似文献
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Serial RapidIO (SRIO) is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check (CRC). In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections. 相似文献
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Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency. 相似文献
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《Microwave Theory and Techniques》1979,27(5):394-399
A Ioad-pull technique utilizing a new method of determining tuner Y parameters is proposed for huge-signal characterization of microwave power transistors. Large-signal input-output transfer characteristics of an active circuit containing a GaAs FET and an input matching circuit are measured by inserting a microstrip tuner between the active circuit output drain terminal and the 50-Omega load. The microstrip-tuner Y parameters are determined by comparing the dc bias-dependent small-signal S parameter S/sub 22/ of the active circuit and that of the circuit which contains the active circuit and microstrip tuner. The reflection coefficient presented to the active circuit output drain terminal is derived from tuner Y parameters. Optimal load impedances for output power, obtained with this new Ioad-pull technique, are used to design X-band GaAs FET power amplifiers. An 11-GHz power amplifier with a 3000-mu m gate-width FET chip delivers 1-W microwave power output with 4-dB gain in the 500-MHz band. 相似文献
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循环冗余校验(CRC)与信道编码的级联使用,可以有效改善译码的收敛特性。在新一代无线通信系统,如5G中,码长和码率都具有多样性。为了提高编译码分段长度可变的级联系统的译码效率,该文提出一种可变计算位宽的CRC并行算法。该算法在现有固定位宽并行算法的基础上,合并公式递推法中反馈数据与输入数据的并行计算,实现了一种高并行度的CRC校验架构,并且支持可变位宽的CRC计算。与现有的并行算法相比,合并算法节省了电路资源的开销,在位宽固定时,资源节约效果明显,同时在反馈时延上也有将近50%的优化;在位宽可变时,电路资源的使用情况也有相应的优化。 相似文献