High Speed Networking Security: Design and Implementation of Two New DDP-Based Ciphers

Using Data-Dependent (DD) Permutations (DDP) as main cryptographic primitive two new ciphers are presented: ten-round Cobra-H64, and twelve-round Cobra-H128. The designed ciphers operate efficiently with different plaintext lengths, 64 and 128-bit, for Cobra-H64 and Cobra-H128, respectively. Both of them use very simple key scheduling that defines high performance, especially in the case of frequent key refreshing. A novel feature of Cobra-H64 and Cobra-H128 is the use of the Switchable Operations which prevent the weak keys. The offered high-level security strength does not sacrifice the implementation performance, of both ciphers. Architecture, design and hardware implementation of the two ciphers are presented. The synthesis results for both FPGA and ASIC implementations prove that Cobra-H64 and Cobra-H128 are very flexible and powerful new ciphers, especially for high-speed networks. The achieved hardware performance and the implementation area cost of Cobra-H64 and Cobra-H128 are compared with other ciphers, used in security layers of wireless protocols (Bluetooth, WAP, OMA, UMTS and IEEE 802.11). From these comparisons it is proven that the two proposed are flexible new ciphers with better performance in most of the cases, suitable for wireless communications networks of present and future.     

Two-step motion estimation algorithm for large search range usingoutlier pixel exclusion

A new two-step motion estimation algorithm is proposed for large search range. It exploits minimum mean-absolute-error quantisation and outlier pixel exclusion to reduce performance degradation. With respect to the full search algorithm, the hardware cost is reduced to 1/144 with similar peak signal-to-noise ratio performance when the search range is ±128×±128     

Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology

In this paper, we characterize the performance of datapath architectures of the Advanced Encryption Standard (AES). These architectures are parameterized by a datapath width of 8, 16, 32, 64, or 128 bits and, for the 128-bit width, an unrolling factor of 1, 2, 5 or 10. Composite field S-boxes are adopted for all the architectures and shift registers based ShiftRows and MixColumns components are used for architectures with datapath widths of less than 128 bits. Their performance in terms of area, peak power and average energy is benchmarked using a 90-nm standard cell CMOS technology under a variety of throughput requirements. Through this characterization, the performance trade-offs affected by the architecture parameters are extensively explored. The parameters leading to the best performance are identified. It is found that the 8-bit width datapath, which is conventionally adopted for resource efficient purposes, has the worst energy efficiency and does not result in the minimal peak power among the architectures. As well, the 16, 32 and 64-bit width AES datapath architectures are newly considered or represent improvements over previous work.     

小型化锑化铟探测器制备

随着红外探测技术的不断发展,市场对红外探测器提出了越来越多的要求,如高分辨率、高工作稳定性、低成本、小型化等,红外探测器光敏芯片的制备技术随之向大面阵、小间距方向不断探索。基于市场需求,本文从技术发展的角度,研究采用离子注入技术、干法刻蚀技术制备台面结型焦平面阵列,实现高性能、窄间距、小型化光敏芯片的制备,为未来高分辨率芯片的制备奠定技术基础。文章介绍了128×128(15μm)、128×128(10μm)两款器件的制备,两款器件中测I-V性能良好,其中,128×128(15μm)器件杜瓦封装组件后性能表现良好。     

AlGaAs/GaAs quantum well infrared photodetector focal plane array based on MOCVD technology

128 × 128, 128 × 160 and 256 × 256 AlGaAs/ GaAs quantum well infrared photodetector (QWIP) focal plane arrays (FPA) as well as a large area test device are designed and fabricated. The device with n-doped back-illuminated AIGaAs/GaAs quantum structure is achieved by metal organic chemical vapor deposition (MOCVD) epitaxial growth and GaAs integrated circuit processing technology. The test device is valued by its dark current performance and Fourier transform infrared spectroscopy (FTIR) spectra at 77 K. Cut off wavelengths of 9 and 10.9 μm are realized by using different epitaxial structures. The blackbody detectivity DB* is as high as 2.6 × 109 cm· Hz1/2·W-1. The 128 × 128 FPA is flip-chip bonded on a CMOS readout integrated circuit with indium (In) bumps. The infrared thermal images of some targets under room temperature background have been successfully demonstrated at 80 K operating temperature. In addition, the methods to further improve the image quality are discussed.     

128?128元双色红外探测器成像电路设计

介绍了针对128×128元双色碲镉汞红外焦平面探测器而设计的一种探测成像系统。该探测成像系统包括探测器适配、视频模拟信号调理、模数转换、非均匀校正以及数字图像输出模块等功能模块。结合光学系统和上位机图像记录软件,对该探测成像系统进行了相关成像试验及性能测试。目前,该探测成像系统已成功应用于红外导引系统。     

Fourth power phase estimation with alternative two-dimensionalodd-bit constellations

It is well established that the fourth power phase estimator does not perform well for QAM cross (i.e., odd-bit) constellations. In this paper, new two-dimensional rectangular constellations are presented that give much improved performance, at a reasonably low increase in required constellation energy. For example, the 128B-COB constellation reduces the variance by an order of magnitude, while increasing the constellation's average energy by only 0.28 dB and the peak to average energy ratio by 1.25 dB, relative to 128-QAM     

A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor

An imager with an integrated fully programmable bit-serial column-parallel processor is proposed to meet the demand for a compact and versatile system-on-imager chip for consumer applications. The on-imager processor is targeting a computationally intensive low-level image processing task. The processor is physically arranged as a densely packed 2-D processing element (PE) array at an imager column level. The digital processor has a multiple-instruction-multiple-data (MIMD) architecture configuring multiple column-parallel single-instruction-multiple-data (SIMD) processors. The prototype imager chip with 128 times 128 pixels and 4 times 128 PE array designed with 0.6-mum technology was fabricated, and its functionality was tested. The estimation of performance level of the proposed processor architecture with an advanced technology such as the 0.09-mum process technology shows that the proposed imager chip architecture has a potential of giga sum operations per second per square millimeter class processing performance.     

基于ATmega 128的高速高精度光功率计的设计

介绍了一套最新研制的高速高精度光功率计的设计方案。该光功率计采用高性能单片机ATmega l28对系统进行控制,以目前业界速度最快16位低功耗、高性能的AD9467为模/数转换器对不同量程的信号进行采集,提高了数据的精度性。通过USB2.0的高速通信能力,充分发挥了ATmega 128的高速采集处理能力。     

一种大面阵红外焦平面阵列读出电路的设计方法

论文提出了一种可用于大面阵红外焦平面阵列的智能化读出电路的设计方法,所设计的读出电路具有放大、读出、片上模数转换以及智能控制等功能。论文主要介绍该面阵电路的组成结构、核心电路的工作原理、电路的仿真方法和结果。通过对该面阵读出电路进行版图设计、流片和性能测试,得到了符合设计要求的面阵规模为128X128的大面阵红外焦平面阵列智能读出电路。     

A growable packet (ATM) switch architecture: design principles andapplication

The problem of designing a large high-performance, broadband packet of ATM (asynchronous transfer mode) switch is discussed. Ways to construct arbitrarily large switches out of modest-size packet switches without sacrificing overall delay/throughput performance are presented. A growable switch architecture is presented that is based on three key principles: a generalized knockout principle exploits the statistical behaviour of packet arrivals and thereby reduces the interconnect complexity, output queuing yields the best possible delay/throughput performance, and distributed intelligence in routing packets through the interconnect fabric eliminates internal path conflicts. Features of the architecture include the guarantee of first-in-first-out packet sequence, broadcast and multicast capabilities, and compatibility with variable-length packets, which avoids the need for packet-size standardization. As a broadband ISDN example, a 2048×2048 configuration with building blocks of 42×16 packet switch modules and 128×128 interconnect modules, both of which fall within existing hardware capabilities, is presented     

高级加密标准AES候选之一--Serpent

介绍了一个新的分组加密算法——Serpent,它是AES的一个候选算法,该算法使用256位的密钥对128位的块数据进行加解密;描述了Serpent的加解密过程及子密钥生成过程,同时对其性能作了部分阐述．     

Large-capacity strictly nonblocking optical cross-connects based onmicroelectrooptomechanical systems (MEOMS) switch matrices: reliabilityperformance analysis

The reliability performance of 128× 128 optical cross-connects (OXCs) based on microelectrooptomechanical systems (MEOMS) switch matrices is considered. First, we compare a strictly nonblocking wavelength selective switch with a strictly nonblocking three-stage Clos architecture. The probability of maintenance of free operation has been investigated for both OXC structures. We present our calculation results for such commonly used reliability measures as mean time between failures (MTBF), mean downtime (MDT) per gear, and steady-state unavailability. It is shown that the reliability performances of the considered OXCs are far from that requested. In this paper, we also investigate possibilities of improving the reliability performance of the considered OXCs by introducing shared redundancy of the MEOMS matrices. We propose two different protection schemes: one for the wavelength selective switch and another for the three-stage Clos architecture. It is shown that the proposed protection schemes significantly improve the reliability performance for both cases. Finally, we compare the performance of the all-optical version of the OXC based on MEOMS matrices with the optoelectronic version of the OXC based on electronic cross-point switch matrices. It is shown that from a reliability viewpoint, the optical cross-connect based on MEOMS matrices is better than that with electrical cross-point switches. The influence of capacity expansion on the system reliability is discussed     

Maximizing Capacity Usage and Selection of Optimal Antennas to Improve Spectrum Efficiency in Massive MIMO Technology

The performance of Massive MIMO can be enhanced by utilizing a large number of antennas than used and signifying its enormous capabilities in upgrading spectral efficiency. Antenna Selection is a low-priced complexity that decreases the number of radiofrequency chains with the contemplation of augmenting channel capacity. In this paper, an Augment Antenna Selection algorithm based on maximum flow minimum cut theorem is proposed which captures the optimal antennas based on the aggregate capacity of the possible antenna combinations. The first step in this algorithm proposes a subset of antennas to compute the augment paths and the second step selection considers the remaining capacity present in antennas to compute the maximum flow in a network. Thus, this algorithm that selects optimal antennas with better channel conditions aims at improving spectrum and energy efficiency. Simulation results show the outage capacity and the performance of BER with 64*64 and 128*128 Massive MIMO versus SNR has been analyzed.

     

高级加密标准AES候选之一--Twofish

介绍了AES的一个候选算法——Twofish,它是一个128位分组加密算法．该密码由一个16圈的Feistel网络构成．描述了Twofish的加解密过程及子密钥生成过程,同时对其性能和抗攻击能力作了分析．     

基于ATmega128的迷你数控雕刻机系统设计

为了实现对迷你数控雕刻机的控制,提出了一种基于ATmega128的迷你数控雕刻机系统设计方案,并完成系统了的硬件电路设计和软件设计.该系统的硬件电路设计部分主要是电源电压转换电路以及以AT-mega128单片机为主控芯片的控制主板与各模块相连电路;软件设计部分主要是利用AVR Studio开发环境编程,实现ATmega128单片机对步进电机、主轴电机、超声波传感器等部件的控制以及实现与PC机握手.重点设计了利用键盘操作板对雕刻头的初步定位系统.实际应用表明,该系统具有操作简便、安全可靠等特点,达到了设计要求.     

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.     

一种基于查找表的移位寄存器链的设计

提出了一种基于查找表的移位寄存器链的设计,以查找表的配置存储单元作为移位模块,以查找表的输入信号作为移位地址选择信号,通过对时钟和写使能的控制进行移位操作。1个查找表最大实现32个时钟周期的移位操作,4个查找表通过配置,可实现4条相互独立的32位移位寄存器链,或首尾级联实现一个128位的移位寄存器链。基于28 nm工艺,对所设计的结构进行了仿真和优化,并对电路进行了多项目晶圆流片。测试结果与仿真匹配良好,实现了32×4和128×1的移位功能,且最高工作频率达到500 MHz,与参考芯片相比,性能提高了10%。     

Design and performance testing of a 2.29-GB/s Rijndael processor

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-/spl mu/m CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.     

Camellia算法及其特性分析

Camellia算法是NESSIE选择的一个128bit的分组加密算法，它与AES一起作为欧洲的加密标准。本文详细介绍了Camellia的基本特征、算法描述及其各种特性。该算法能适合不同的软硬件平台，实现方便，速度快，能对抗已知的各种攻击。