Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.     

Sensor for monitoring the rinsing of patterned wafers

Developing efficient wafer cleaning and rinsing requires technology for on-line monitoring of the wafer cleanliness. An electrochemical sensor is designed, fabricated, and tested to measure the concentration of residual contaminants on the wafer surface during the rinse process. The sensor is based on the real time and in situ measurement of electrical impedance across a trench microstructure. The sensor's output signal is proportional to the concentration of impurities remaining in the trench and, therefore, is a measure of the progress of the rinse in cleaning the wafer surface. Electrical measurements, circuit analysis, and direct testing of the device at known impurity levels are used to select and design a suitable sensor configuration. The results confirm the feasibility and sensitivity of the device applicable to typical wafer rinsing conditions.     

Megasonic cleaning: A new cleaning and drying system for use in semiconductor processing

A compact system for cleaning wafers in all stages of device manufacture has been developed which uses high frequency (0.8 to 1 MHZ) ultrasonic energy (hence, the term “Megasonic”) and a standard chemical solution which is not heated. The patented process effectively removes particles down to approximately 0.3 ym diameter simultaneously from the front and back surfaces, thin organic films, and many ionic impurities. After a brief water rinse, the wafers are dried in a hot air stream. The total cycle time is approximately 15 minutes, and at least 100 wafers can be cleaned in quartz or plastic carriers at the same time and without the need for loading or unloading. Megasonic cleaning has been applied to silicon wafers, ceramics, and photomasks, and has been used for photo- Paper presented at 20th Annual Electronic Materials Conference, University of California at Santa Barbara, CA, June 30, 1978.     

硅晶片表面污染物去除的关键工艺

硅晶片的清洗通常是在一个“过流(overflow)”清洗槽中进行,其中流过晶片的水流平均速度为1cm蛐s,而在晶片表面的速度则为零。清洗效率受到污染物从硅片表面扩散出并进入到水流速率的限制。报告了清洗效率的提高熏通过对初次将污染物扩散进停滞层的1min循环进行重复,然后“倾倒”清洗槽,从而去除大部分污染的停滞层。通过旋转晶片,并利用离心力去除更大部分的停滞层,每个清洗循环可将清洗效率再提高10倍眼1演。与目前的浸泡式清洗技术相比,本方法可以完全去除可溶性污染物,而使用的水量降低20倍。     

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50 kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200 mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50 nm.     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

Fabrication of low-cost mold and nanoimprint lithography using polystyrene nanosphere

The periodic arrays of nanostructure were successfully patterned on Si wafers by ultraviolet nanoimprint lithography (UV-NIL) using nanosphere lithography (NSL). Two-dimensional (2D) well ordered self-assembled arrays were obtained on Si wafer by using nanosphere and the tilted-drain method. We tried to combine two techniques and hard mold of Si mold for NIL and polymer mold of acrylate-based polymer were fabricated by NSL. The Si master mold and polymer mold were formed by Cr lift-off and ICP-RIE process. The surface has a low surface energy at the interface with 1H, 1H, 2H, 2H-perfluorooctyl-trichlorosilane (FOTS) vapor-coating, which can eliminate the problem of the adherence to the surface of the mold during demolding. Finally, nanopatterns were formed by UV-NIL, where the residual layer was not observed.     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Correlation analysis between pattern and non-pattern wafer for characterization of shallow trench isolation–chemical–mechanical polishing (STI–CMP) process

This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, the removal properties of plasma enhanced tetra-ethyl ortho-silicate (PETEOS) blanket wafers was investigated, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the amount of oxide removal by blanket and patterned wafers. We analyzed this relationship, and the post-CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafers (correlation factor: 0.7109). So, we could confirm the repeatability as applying to STI CMP process from the linear formula obtained.     

Optical,non-destructive characterization of ultra-shallow junctions

As ULSI technology moves below the 180 nm technology node, tight control of the depth of ultra-shallow junctions (USJ), such as those used in source-drain extensions, becomes critical. The problem is one of both local control and uniformity over the full area of 200 and 300 mm wafers. This paper describes the status of carrier illumination™ (CI), an optical method for measuring the active junction depth for ultra-shallow source-drain extensions. It features a non-destructive, high throughput measurement with a spot size of less than 2 μm. This provides rapid uniformity measurements on patterned wafers, enabling in-line control of USJ processes. CI is based on injecting excess carriers that line up with the active doping profile. These carriers act as a “contrast agent” allowing an optical interferometer to measure their profile. The active junction depth may then be deduced from the interferometer signal. This paper first describes the CI measurement and motivation for its development. It then presents a summary of qualification results on PMOS and NMOS process flows. These demonstrate use of the measurement at the process steps associated with extension and source/drain (SD) formation, on both bare and patterned wafers. Correlation is shown to SIMS, SRP, sheet resistance, and transistor and test structure electrical measurements.     

Effects of surface preparation on the electrical and reliabilityproperties of ultrathin thermal oxide

A new wafer cleaning procedure has been developed for ultrathin thermal oxidation process (⩽50 Å). It consists of a conventional RCA clean and a two-dip step, first in diluted HF and then in a methanol/HF solution, with no final DI water rinse. The effectiveness of this cleaning process has been compared to other commonly used cleaning methods, based on the dielectric integrity of the ultrathin thermal oxide grown. It has been found that this two-dip method produces oxides with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxide. Furthermore, this new procedure increases dielectric breakdown field, E_bd and charge-to-breakdown, Q_bd (both intrinsic and defect-related values) of ultrathin oxides. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen and the reduced surface micro-roughness     

Water sensor with optical fiber

In optical-fiber networks, it is important to monitor water which seeps into splice enclosures. The fibers have residual stress at splicing points, and when water is present, this adversely affects fiber lifetime. A water sensor which has a simple structure for monitoring water at splicing points has been developed. This water sensor causes optical loss due to fiber bending when water seeps into splicing enclosures. The design method using a fiber-bending model and sensor performance are described     

300 mm Si片加工及最新发展

65 nm及以下线宽对Si片表面的各方面性能要求越来越高,主要体现在两个方面,一个是加工工艺,另一个是加工设备.在加工方法上,65 nm线宽用300 mm Si片不同于90 nm,如运用多步单片精密磨削,不仅可以提高表面几何参数,还可以减小表面特别是亚表面的损伤层.而对于加工设备,要求更加精密,特别是单面精抛光,在保证去除量的同时还要使Si片表面各点的去除量保持均匀.对目前300 mm Si片的磨削、抛光及清洗的每一道工艺流程,特别是相对于65 nm技术的一些加工流程及方法的最新发展进行了详细的论述,指出了300 mm Si片加工工艺的发展趋势.     

Silicide pre-clean effects on NiPtSi thermal stability for 65 nm technologies and beyond

The effects of different surface preparations on NiPtSi thermal stability were studied. HF wet clean, argon sputter etch and remote plasma pre-clean were used as silicide pre-cleans prior to NiPt sputter deposition and subsequent silicidation on blanket and patterned Si wafers. NiPtSi was characterized using SIMS, ellipsometry, voltage contrast (ES25) testing and electrical performance measurements of 65 nm test structures. Results show that when an in situ remote plasma pre-clean is used in addition to a classical HF wet clean to remove native oxide from the Si substrate prior to NiPt deposition and silicidation, Rs uniformity and SRAM electrical performance as a function of thermal budget are significantly improved. Rs measurements of patterned wafers and SIMS analysis of blanket wafers strongly suggest that the absence of native oxide prior to NiPt deposition and the presence of fluorine at the NiPtSi/Si interface play a key role in improving NiPtSi thermal stability.     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

Characterization and modeling of oxide chemical-mechanicalpolishing using planarization length and pattern density concepts

Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. In the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length     

Multilevel metal interconnection utilizing CVD tungsten and liftoff processing

Interconnections between semiconductor devices in integrated circuits continue to present difficult problems in the tradeoffs between RC time constants, production worthiness, reliability, structural complexity, and compactibility for any single technology. A process and structure has been demonstrated for integrated circuit interconnections which uses a conformai tungsten layer deposited by chemical vapor deposition to provide step coverage into via holes of variable height. The film is then patterned with a via interconnect pattern designed for liftoff processing, layers of chromium copper and chromium are then depositedinsitu on the wafers by way of evaporation. The undesired material is lifted off in a solvent process and the resulting metal pattern is used as the mask for the reactive ion etching of CVD tungsten. This combination of materials and process allows for high conductivity reliable interconnections with negligable step coverage problems. Processing and test information will be presented in the paper.     

锗抛光片干燥技术研究

在锗加工工艺中,干燥技术对于加工的成品率和抛光片表面质量有着重要的影响。介绍了异丙醇脱水干燥技术的原理,分析了异丙醇脱水技术对超薄锗抛光片的适用性。采用湿法清洗技术,有效去除了表面沾污和抛光后的表面氧化产物,控制了抛光片表面GeO_2的生成。采用异丙醇脱水技术成功实现了140μm厚锗抛光片的干燥。