nMOSFET低能X射线辐照特性研究

讨论了MOSFET的辐照损伤机理,通过低能（10keV）X射线辐照试验,分析了不同X射线辐照总剂量、不同剂量率对nMOSFET单管的转移特性以及阈值电压的影响。结果表明X射线辐照对nMOSFET的阈值电压变化的影响与^60Co辐照影响的规律基本一致。     

SOS晶体管中γ射线辐照损伤退火的温度关系

本文研究了n沟SOS晶体管中γ射线辐照损伤无偏置退火的温度关系。研究发现,当辐照产生的氧化层俘获电荷多于界面态电荷时,等温退火会导致界面态电荷增加。界面态电荷是氧化层俘获电荷转变成界面态电荷造成的。阈值电压退火的速率限制阶段便是这一转变阶段。在辐照明显引起界面态电荷时,辐照引起的界面态电荷在高温下退火会立即消除,但也发现了氧化层俘获电荷向界面态电荷转变这一现象。因此,高温下界面态退火的特性就变得复杂起来。辐照之后阈值电压的不稳定性归固于界面态的增减。     

偏置条件对NMOS器件X射线总剂量效应的影响

采用10 keV X射线,对NMOSFET在不同偏置条件下进行总剂量辐射,分析了辐照前后辐射感生的氧化物陷阱电荷与界面态电荷对MOS器件阈值电压的影响以及辐射导致漏电现象.实验结果表明,对于NMOSFET,On偏置条件是最劣偏置条件,Off偏置条件是最优偏置条件.     

低能X射线对NMOST的辐照损伤及退火特性

本文研究了NMOS晶体管低能X射线辐照后氧化物陷阱电荷的产生、界面态的性质及空穴陷阱的退火特性等问题。实验结果表明,电离辐照产生的界面态具有施主性和受主性,而氧化物陷阱电荷引起的电压变化在退火过程中,随外加偏置电场极性的不同,表现出可逆性,它对晶体管阈值电压的变化起着决定性的作用。     

部分耗尽型注氟SIMOX器件的电离辐射效应

采用在SIMOX圆片埋氧层中注入氟(F)离子的方法改善SIMOX的抗总剂量辐射能力,通过比较未注F样品和注F样品辐照前后SIMOX器件Ids-Vgs特性和阈值电压,发现F具有抑制辐射感生pMOSFET和nMOSFET阈值电压漂移的能力,并且可以减小nMOSFET中由辐照所产生的漏电流.说明在SOI材料中前后Si/SiO2界面处的F可以减少空穴陷阱密度,有助于提高SIMOX的抗总剂量辐射能力.     

不同结构nMOS管的总剂量辐射效应北大核心CSCD

X射线直接成像的CMOS图像传感器由于工作在X射线辐射下,其内部器件会因为辐射效应引起性能恶化,因此需要对器件进行抗辐射加固并研究辐射对器件参数的影响。辐射导致的氧化物陷阱电荷及界面陷阱电荷受到栅氧厚度、偏置电压大小、辐射总剂量以及剂量率等多种因素影响。设计了n型场效应晶体管辐射加固结构版图,用0.5μm CMOS工艺流片,并进行了30 kGy(Si)的总剂量辐照效应实验。实验结果显示,所设计的n型场效应晶体管在辐射之后漏电流有所增加、跨导减小、阈值电压向负向漂移;辐射加固晶体管在漏电流性能上较未加固晶体管更好,在跨导改变和阈值电压漂移上未能表现出其更优的性能。     

不同结构nMOS管的总剂量辐射效应

X射线直接成像的CMOS图像传感器由于工作在X射线辐射下,其内部器件会因为辐射效应引起性能恶化,因此需要对器件进行抗辐射加固并研究辐射对器件参数的影响。辐射导致的氧化物陷阱电荷及界面陷阱电荷受到栅氧厚度、偏置电压大小、辐射总剂量以及剂量率等多种因素影响。设计了n型场效应晶体管辐射加固结构版图,用0.5μm CMOS工艺流片,并进行了30 kGy(Si)的总剂量辐照效应实验。实验结果显示,所设计的n型场效应晶体管在辐射之后漏电流有所增加、跨导减小、阈值电压向负向漂移;辐射加固晶体管在漏电流性能上较未加固晶体管更好,在跨导改变和阈值电压漂移上未能表现出其更优的性能。     

N沟MOSFET／SIMOX的γ射线辐照特性

对用多次注入与退火技术制成的ＳＩＭＯＸ材料制备的Ｎ沟ＭＯＳＦＥＴ进行了＾６０Ｃｏγ射线累积剂量辐照试验，并同通常的体硅ＮＭＯＳ的辐照效应作了比较，分析了引起阈值电压漂移的两个因素：氧化层电荷和界面态电荷，提出了提高ＮＭＯＳ／ＳＩＭＯＸ抗辐照性能的几点措施。     

不同偏置条件下PMOSFETs的剂量率效应研究

研究了不同剂量率、不同偏置条件下,PMOSFETs的辐照响应特性;并对高剂量率辐照后的器件进行了与低剂量率辐照等时的室温退火。结果表明,随着剂量率的降低,PMOSFETs阈值电压的漂移更加明显;不同偏置条件、不同剂量率范围内表现出TDE和ELDRS两种不同的剂量率效应。利用亚阈分离技术对影响阈值电压漂移的氧化物陷阱电荷和界面态进行了详细的机理分析,认为ELDRS效应的产生是由界面态密度的差异导致的。     

动态阈值nMOSFET阈值电压随温度退化特性

对动态阈值nMOSFET阈值电压随温度退化特性进行了一阶近似推导和分析。动态阈值nMOSFET较之普通nMOSFET,降低了阈值电压温度特性对温度、沟道掺杂浓度及栅氧厚度等因素的敏感程度。讨论了动态阈值nMOSFET优秀阈值电压温度特性的内在机理。动态阈值nMOSFET优秀的阈值电压随温度退化特性使之非常适合工作于高温恶劣环境。     

A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation(STI) stress has been developed.The model is verified by 130 nm technology layout dependent measurement data.The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET.The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11%improvement of average delay time.This indicates the importance of STI stress consideration in circuit design.     

STI应力效应下的pMOSFET阈值电压物理模型

本文提出了浅沟道隔离（STI）应力效应下的P型MOSFET的阈值电压物理模型,并用不同STI版图位置的130纳米的器件数据进行了验证。基于此STI阈值电压模型,我们对比了p型MOSFET和n型MOSFET在STI应力下的阈值电压和迁移率的变化。数据表明,相比n型MOSFET,p型MOSFET的阈值电压更少地受到STI应力影响,但迁移率却更多地受到STI应力影响。基于此STI阈值电压模型,我们进行了九级震荡环电路的模拟。模拟数据显示,适当的STI应力能使电路平均延迟时间提高约11%,同时也说明了STI应力模型在电路设计中的重要性。     

Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD$hboxHfO_2$has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation.     

MOSFET中热载流子效应的计算、实验和模拟

亚微米 MOSFET的热载流子效应会引起器件的失效 ,文中分析了热载流子效应引起器件失效的机理和物理模型 ,对该效应的内部电场、衬底电流、阈值电压和跨导作了计算 ;使用知名的集成电路器件模拟软件 ATL AS模拟了该效应 ;并对实际 MOSFET作了 I- V特性曲线和跨导变化量随偏压时间变化的实验测试。理论分析、实验结果与模拟结果都符合得很好。为改善MOSFET热载流子效应而提出的 GOL D结构也获得很好的模拟结果。     

反应离子刻蚀铝中nMOS 器件的等离子充电损伤

介绍在等离子工艺中的等离子充电损伤,并且利用相应的反应离子刻蚀(RIE)Al的工艺试验来研究在nMOSFET器件中的性能退化。通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。在现有的理解上对在RIEAl中nMOS器件等离子充电损伤进行了讨论,并且基于这次试验结果对减小等离子损伤提出了一些建议。     

Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.     

Parametric expression of subthreshold slope using threshold voltageparameters for MOSFET statistical modeling

In this paper, we propose a newly developed subthreshold slope (ideality factor) model, whose parameters are solely determined from the threshold voltage data. We succeed in expressing the ideality factor in terms of the threshold voltage parameters obtained from the body and DIBL effects, which can take care of its dependence on the process data such as channel length, oxide thickness, substrate doping profile, and junction depth in a parametric way. We prove the validity of our model by comparing it with simulation and measurement results from nMOSFET devices with various oxide thickness, channel length, and doping profile     

Damage to insulated gate FETs by electron beam metrology and X-ray exposure

A comparison of the damage induced by X-rays and electron-beam radiation on IGFETs has been made. It is observed that the ratio of the threshold voltage shift due to fixed positive charge (ΔV _FPC) to the total threshold voltage shift (due to both fixed positive charge and neutral electron traps) does not show any dependence on the radiation dose in the case of an E-beam irradiation, and shows a negative slope for X-ray irradiated samples. This suggests that the amount of neutral electron traps (NETs) and fixed negative charge (FNC) produced by the ionizing radiation is higher in the case of X-ray irradiation and saturates at much higher doses compared to E-beam irradiation. A study of electron beam damage at various energies shows that E-beam energy of 7 keV does not damage the oxides at all whereas at lOkeV maximum damage is observed. For devices exposed to X-rays, the threshold voltage shift ratios due to the fixed positive charge for different gate oxide thicknesses (12·6nm-50·0nm) indicate a shift of the effective charge centre-id which also depends on the filling of neutral electron traps to form fixed negative charges that partially compensate the fixed positive charges. The threshold voltage shift ratios also indicate a shift in the charge centroid which is pronounced in the thinner oxides. A model for the change in effective centroid of charge and also its dose dependence for different oxide thicknesses has been suggested.     

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.