New Lossless Turn-On and Turn-Off (Snubber) Networks for Inverters, Including Circuits for Blocking Voltage Limitation

Transistorized pulsewidth modulated (PWM) inverters require careful dimensioning of turn-on and turn-off circuits in order to minimize switching loss in the power transistors. New lossless circuits are described. In particular the turn-off circuits show a highly reduced part count compared to circuits known from the literature. The turn-on circuits apply energy recovery. Furthermore, due to a special circuit the voltage across the power transistor is strictly limited. This is important especially due to the usually low voltage blocking capability of high-current power transistors.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Employing multiple supply voltages (multi- V_DD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-V_th) level converters are proposed in this paper. The new multi-V_th level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.     

Internal voltage generator for low voltage, quarter-micrometerflash memories

A fabricated bandgap generator using 0.25-μm Flash memory process generated a stable reference voltage under 4 V, boosted from an external power supply of 2.5 V. The generated voltage was 1.297±0.025 V at a power supply of 4 V±10%; the temperature dependence was +0.7 mV/°C. The characteristics of a triple-well bipolar transistor for the Flash memory process are sufficient for a reference voltage generator; f_T is 230 MHz, and H_FE is 70. Dynamic operation reduced the average current consumption from 306 to 8.6 μA. Fabricated voltage-doubler circuits generated a voltage 1.8 times larger than that from conventional charge-pump circuits     

低耗低纹波可控式APD偏置电路

给出了两种非常适合作为APD偏置电路的高效、低耗、低纹波输出、可控式高压发生电路,同时给出了电路的应用说明.     

高压大功率器件小电流控制技术研究

随着高压大功率双极功率集成电路在各种电源管理、功率驱动等领域中的应用日益广泛,产品的可靠性设计和控制显得尤其重要.介绍了高压大功率器件小电流的控制研究,说明了小电流形成的原理,及其对产品可靠性的影响;对各类曲线进行了详细分析,阐明了小电流的测试和控制技术,以及小电流对高压大功率双极型集成电路可靠性的重要性.     

设计高频高压场效应晶体管的一些考虑

高频高压场效应晶体管(LDMOS)是功率MOS器件中同时具有高频高压性能的一种器件,也是目前广泛用于HVIC(高压集成电路)及PIC(功率集成)电路的器件之一。本文从结构上描述了器件的高频、高压特性,并提出了一些可提高这些性能的措施和设计思想。     

Simultaneous power supply, threshold voltage, and transistor sizeoptimization for low-power operation of CMOS circuits

This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

A fully digital, energy-efficient, adaptive power-supply regulator

A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits. A digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented. This paper investigates the issues involved in designing a fully digital power converter and describes a design fabricated in a MOSIS 0.8-μm process. A variable-frequency digital controller design takes advantage of the power savings available through adaptive supply-voltage scaling and demonstrates converter efficiency greater than 90% over a dynamic range of regulated voltage levels     

Design, fabrication, and performance of scaled analog ICs

This paper concerns scaled MOS circuits for high-speed and high-density analog LSIs. The effect of scaling the devices employing three different scaling laws (constant electric field, constant voltage, and quasiconstant voltage laws) is examined using both the first-order approximation and two-dimensional device simulator. Versatile scaling relationships for analog circuits are then developed. They show that the bandwidth, transient response, and low-frequency gain are generally improved; however, the signal-to-noise ratio (S/N) is reduced by a scaling factor of k/SUP 0.5/ or k depending on which scaling law is used. To further investigate the scaling effects, scaled NMOS op amps are developed based mainly on the quasi-constant voltage law with k of approximately 2 and 3 compared to the conventional 8.5 /spl mu/m rule NMOS op amp. Improvements in slew rates and gain-bandwidth products are more than sixfold while keeping the low-frequency open-loop gain, power dissipation, and S/N almost unchanged.     

Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects

The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high performance, low power, and low area on wave-pipelined interconnect circuits. Based on this methodology, design optimizations for three different types of applications are performed and different design metrics are used to obtain the optimal values of supply voltage, number of repeaters, and interconnect dimensions for these applications. The optimal supply voltage for low-power applications is shown to be twice the threshold voltage. In addition, an optimal throughput-per-energy-area (TPEA) design is compared with low-voltage differential signaling (LVDS). The optimal TPEA design is shown to reduce dynamic power by 10% and wire area by 70% compared to LVDS, without any loss of throughput performance.     

低压、低功耗SOI电路的进展

最近 IBM公司在利用 SOI(Silicon- on- insulator)技术制作计算机中央处理器 (CPU)方面取得了突破性的进展 ,该消息轰动了全世界。SOI电路最突出的优点是能够实现低驱动电压、低功耗。文中介绍了市场对低压、低功耗电路的需求 ,分析了 SOI低压、低功耗电路的工作原理 ,综述了当前国际上 SOI低压、低功耗电路的发展现状。     

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V_dd², decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.     

一种压电陶瓷微位移器驱动电源研究

在研究压电陶瓷微位移器的基础上,针对压电陶瓷的驱动特点和要求,设计了一种驱动电源。以单片机Atmega128和高压运算放大器PA78为核心器件,以及相关电路构成电压控制型驱动电源。介绍了主要模块电路的功能和实现,并对驱动电源进行测试实验。驱动电源可输出0~300 V连续电压,分辨率可达10 mV、静态纹波＜5 mV。结果表明该电源具有线性度高、稳定性好、分辨率高等优点。     

电压倍增之像素设计

为了节省面板电路驱动芯片的功率损耗以及制作成本,本研究提出一种新的像素电路设计,而在设计中将会融合电荷泵电路。利用这种电路设计的像素可有效地将像素电极上的驱动电压提高到输入电压的2～3倍以上。此像素电路设计具有两个优势:第一,可以有效降低显示面板的像素功率损耗;第二,不需高电压的面板电路驱动芯片,因此可节省芯片的成本及功率损耗。由模拟结果可知,像素电极上的驱动电压确实可由此像素电路设计而提高到输入电压的2～3倍以上;而像素的功率损耗也可有效地降低,约为传统像素的1/2。     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

Differential current switch logic: a low power DCVS logic family

Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights