Emulating switch-level models of CMOS circuits

This paper presents a method for emulating switch-level models of CMOS circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. The method presented in this paper, unlike the abstraction methods, can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the remaining parts of the circuit are emulated at the gate-level. The experimental results show that the presented emulation-based approach could be significantly faster than existing simulation-based approaches. The analytical performance estimation shows that the speed-up grows with the circuit size and is workload dependent.     

A dynamic CMOS multiplier for analog VLSI based on exponentialpulse-decay modulation

A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Stuck fault test generation for dynamic CMOS

In this paper, a procedure that utilizes a previously introduced LTF model is used to detect classical and non-classical faults. Logic Transistor Function (LTF) was devised to model the dynamic CMOS combinational circuit at the transistor-logic level. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF. The model uses four logic levels (0,1,M,I) where I and M imply an indeterminate logical value and a memory element, respectively. A systematic procedure is presented to produce the faulty D-cube for a faulty dynamic CMOS gate, by using LTF technique. For test generation algorithm, a variant of the D-algorithm is applied to sensitize the fault effect to an observable output. Both combinational and sequential D-cube may be conceived by using this procedure.     

CMOS analog/digital circuit of the hysteresis McCulloch-Pitts neuron for Ramsey numbers

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCulloch-Pitts binary neuron found five Ramsey numbers. The analog CMOS sigmoid circuit with variable gain controls has been fabricated and tested using the SAC data acquisition board interfaced with a TMS 32010 processor. Hysteresis can be implemented by the positive feedback in the fabricated CMOS analog circuit.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

Analysis and reduction of signal readout circuitry temporal noisein CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 μm CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data     

Simple optimising methodology for static frequency divider design

An optimising method to improve the speed of a source-coupled-logic static frequency divider is presented. A piecewise linear transistor model is applied to simplify the large-signal analysis. The optimised circuit parameters can be quickly estimated from the analysis result. The simulation and measurement results on a 0.35 mum CMOS process have been used to demonstrate this optimisation method     

Numerical Design Optimization Methodology for Wideband and Multi-Band Inductively Degenerated Cascode CMOS Low Noise Amplifiers

In this paper, we develop a systematic design optimization methodology for inductively degenerated cascode CMOS low noise amplifiers (LNA) in fully integrated wideband and multi-band wireless systems. Leveraging an accurate analytical circuit model, we combine global and local numerical optimization techniques in a hierarchical manner to simultaneously determine the fixed and switchable passive component and device parameters in the LNA circuit necessary to meet user-specified performance requirements. To demonstrate the effectiveness of proposed design optimization methodology, we utilize the method to create 3 wideband and 3 multi-band LNA designs that meet a wide-range of impedance matching, noise figure, gain, power dissipation, and linearity requirements. The proposed method provides circuit designers with a fast and effective means for the rapid prototyping and design space exploration of wideband and multi-band inductively degenerated cascode CMOS LNAs.      

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Design optimization of JCMOS structures

JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure.     

A transient analysis of latchup in bulk CMOS

This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.     

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.     

An energy-efficient spike encoding circuit for speech edge detection

In speech processing applications, the instantaneous bandwidth of speech can be used to adaptively control the performance of an audio sensor’s analog front end. Extracting the instantaneous bandwidth of speech depends on the detection of speech edges in the time–frequency plane. In this paper, we propose a spike encoding circuit for real-time and low-power speech edge detection. The circuit can directly encode the signal’s envelope information—an important feature to identify the speech edge—by temporal spike density without additional envelope extraction. Furthermore, the spike encoding circuit automatically adapts its resolution to the amplitude of the input signal, which improves the encoding resolution for small signal without increasing the power consumption. We use the nonlinear dynamical approach to design this circuit and analyze its stability. We also develop a linearized model for this circuit to provide the design intuition and to explain its adaptive resolution. Fabricated in 0.5-μm CMOS process, the spike encoding circuit consumes 0.3-μW power and the experimental results are presented.     

Scalable wideband equivalent circuit model for silicon-based on-chip transmission lines

A scalable wideband equivalent circuit model of silicon-based on-chip transmission lines is presented in this paper along with an efficient analytical parameter extraction method based on improved characteristic function approach, including a relevant equation to reduce the deviation caused by approximation. The model consists of both series and shunt lumped elements and accounts for high-order parasitic effects. The equivalent circuit model is derived and verified to recover the frequency-dependent parameters at a range from direct current to 50 GHz accurately. The scalability of the model is proved by comparing simulated and measured scattering parameters with the method of cascade, attaining excellent results based on samples made from CMOS 0.13 and 0.18μm process.     

硅基平面螺旋电感的等效电路模型和参数提取

针对螺旋电感传统等效电路模型的不足,提出了一种改进形式的集总参数等效电路模型.该等效电路模型能很好地反映出电感参数随频率变化的实际效应,可适用于从低频到自谐振频率的宽频带范围.同时,应用电磁场全波分析方法对CMOS工艺下平面螺旋电感进行仿真分析.从得到的散射参数中提取电感L、Q值及自谐振频率.基于参数优化和曲线拟合技术,给出了等效电路模型中各个元件值的多变量闭合表达式.这些表达式可方便地用于集成电路的设计和优化,从而提高电路设计的性能和效率.     

射频CMOS平面螺旋电感2-π等效电路模型参数的提取

从有理分式拟合方法出发,提出了用于射频CMOS平面螺旋电感2-π等效电路模型参数提取的新方法.通过比较提参后等效电路给出的S参数和实验测量的S参数,证明该方法的精度很高.此外,提参的策略非常直接,因此容易在CAD里面编程实现.提参得到的等效电路模型对于射频电路设计者来说也是非常有用的.     

低电压下CMOS数字电路概率模型研究

为解决数字电路低功耗问题,电路工作电压被不断降低,导致电路逻辑器件呈现概率特性。本文提出了低电压下CMOS数字电路的错误概率模型,并完成硬件电路测试验证。本文首先详述了深亚微米（DSM）量级的门电路及模块在低电压供电条件下导致器件出错的因素,结合概率器件结构模型推导基本逻辑门概率模型,并提出了状态转移法用于完成由门级到模块级的概率分析模型;我们搭建硬件平台对CMOS逻辑芯片进行了低供电压测试,通过分析理论推导结果与实测结果,验证并完善了分析模型。实验结果表明,由状态转移法推导的电路概率模型符合电路实际性能,从而为构建低电压下数字电路概率模型提供了可靠分析模型。      

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.