Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

Low power resistive switching memory using Cu metallic filament in Ge0.2Se0.8 solid-electrolyte

Bipolar resistive switching memory device using Cu metallic filament in Au/Cu/Ge_0.2Se_0.8/W memory device structure has been investigated. This resistive memory device has the suitable threshold voltage of V_th > 0.18 V, good resistance ratio (R_High/R_Low) of 2.6 × 10³, good endurance of >10⁴ cycles with a programming current of 0.3 mA/0.8 mA, and 5 h of retention time at low compliance current of 10 nA. The low resistance state (R_Low) of the memory device decreases with increasing the compliance current from 1 nA to 500 μA for different device sizes from 0.2 μm to 4 μm. The memory device can work at very low compliance current of 1 nA, which can be applicable for extremely low power-consuming memory devices.     

A novel organic electrical memory device based on the metallofullerene-grafted polymer (Gd@C82-PVK)

The ITO/Gd@C₈₂-PVK/Al sandwich nonvolatile memory device was developed based on polymer containing carbazole moieties as electron donors and Gd@C₈₂ as electron acceptors for the first time. The results of I–V characteristic test indicated that the new material exhibited typical bistable electrical switching and a nonvolatile rewritable memory effect, with a turn-on voltage of about −1.5 V and an ON/OFF-state current ratio of more than 10⁴. We propose that such a low turn-on voltage is caused due to the encaged metal and the DFT calculation indicated that the encaged metal served as an important electron trapping center, which facilitated the arrival of turn-on voltage.     

Si-nanoclusters embedded into epitaxial rare earth oxides: Potential candidate for nonvolatile memory applications

Using an unconventional approach, single crystalline Si-nanoclusters (Si-NCs) with uniform size and higher density were embedded into epitaxial rare earth oxide with two-dimensional spatial arrangements at a defined distance from the substrate using solid source molecular beam epitaxy (MBE) technique.The incorporated Si-NCs with average size of 5 nm and density of 2 × 10¹² cm⁻² exhibit charge storage capacity with promising retention (∼10⁷ s) and endurance (10⁵ write/erase cycles) characteristics. The Pt/Gd₂O₃ (Si-NC)/Si (MOS) basic memory cells with embedded Si-nanoclusters display large programming window (∼1.5-2 V) and fast writing speed. With such properties demonstrated, we believe that the Si-NCs embedded in epitaxial Gd₂O₃ could be potential candidate for high density nonvolatile memory devices in the future.     

An Ultrafast Nonvolatile Memory with Low Operation Voltage for High-Speed and Low-Power Applications

Memory plays a vital role in modern information society. High-speed and low-power nonvolatile memory is urgently demanded in the era of big data. However, ultrafast nonvolatile memory with nanosecond-timescale operation speed and long-term retention is still unavailable. Herein, an ultrafast nonvolatile memory based on van der Waals heterostructure is proposed, where a charge-trapping material, graphdiyne (GDY), serves as the charge-trapping layer. With the band-engineered heterostructure and excellent charge-trapping capability of GDY, charges are directly injected into the GDY layer and are persistently captured by the trapping sites in GDY, which result in an ultrafast writing speed (8 ns), a low operation voltage (30 mV), and a long retention time (over 10⁴ s). Moreover, a high on/off ratio of 10⁶ is demonstrated by this memory, which enables the achievement of multibit storage with 6 discrete storage levels. This device fills the blank of ultrafast nonvolatile memory technology, which makes it a promising candidate for next-generation high-speed and low-power-consumption nonvolatile memory.     

Characteristics of chalcogenide nonvolatile memory nano-cell-element based on Sb2Te3 material

Phase-change nonvolatile memory cell elements composed of Sb₂Te₃ chalcogenide have been fabricated by using the focused ion beam method. The contact size between the Sb₂Te₃ phase change film and electrode film in the cell element is 2826 nm² (diameter: 60 nm). The thickness of the Sb₂Te₃ chalcogenide film is 40 nm. The threshold switching current of about 0.1 mA was obtained. A RESET pulse width as short as 5 ns and the SET pulse width as short as 22 ns for Sb₂Te₃ chalcogenide can be obtained. At least 1000 cycle times with a RESET/SET resistance ratio >30 times is achieved for Sb₂Te₃ chalcogenide C-RAM cell element.     

Nonvolatile memory and opto-electrical characteristics of organic memory devices with zinc oxide nanoparticles embedded in the tris(8-hydroxyquinolinato)aluminum light-emitting layer

The nonvolatile organic memory devices based on the tris(8-hydroxyquinolinato)aluminum (Alq₃) emitting layer embedded with zinc oxide nanoparticles (ZnO-NPs) are reported. The devices have a typical tri-layer structure consisting of the Alq₃/ZnO-NPs/Alq₃ layers interposed between indium tin oxide (ITO) and aluminum (Al) electrodes. An external bias is used to program the ON and OFF states of the device that are separated by a four-orders-of-magnitude difference in conductivity. No significant degradation of the device is observed in either the ON or OFF state after continuous stress (∼10⁵ s) and multicycle (∼10³ cycles) testings. These nanoparticles behave as the charge trapping units, which enable the nonvolatile electrical bistability when biased to a sufficiently high voltage. Impedance spectroscopy, capacitance–voltage (C–V) and current–voltage (I–V) analysis are used to verify the possible physical mechanism of the switching operation. Moreover, it is found that the location of the ZnO-NPs could affect the memory and opto-electrical characteristics of the devices, such as the ON/OFF ratio, threshold voltage and turn-on voltage, which can be attributed to the influence of the ZnO-NPs and diffused Al atoms in the bulk of the Alq₃ layer.     

Characterization of PI:PCBM organic nonvolatile resistive memory devices under thermal stress

In this study, we fabricated nonvolatile organic memory devices using a mixture of polyimide (PI) and 6-phenyl-C61 butyric acid methyl ester (PCBM) (denoted as PI:PCBM) as an active memory material with Al/PI:PCBM/Al structure. Upon increasing the temperature from room temperature to 470 K, we demonstrated the good nonvolatile memory properties of our devices in terms of the distribution of ON and OFF state currents, the threshold voltage from OFF state to ON state transition, the retention, and the endurance. Our organic memory devices exhibited an excellent ON/OFF ratio (I_ON/I_OFF > 10³) through more than 200 ON/OFF switching cycles and maintained ON/OFF states for longer than 10⁴ s without showing any serious degradation under measurement temperatures up to 470 K. We also confirmed the structural robustness under thermal stress through transmission electron microscopy cross-sectional images of the active layer after a retention test at 470 K for 10⁴ s. This study demonstrates that the operation of PI:PCBM organic memory devices could be controlled at high temperatures and that the structure of our memory devices was maintained during thermal stress. These results may enable the use of nonvolatile organic memory devices in high temperature environments.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

Nonvolatile Ferroelectric Memory Effect in Ultrathin α‐In2Se3

High‐density memory is integral in solid‐state electronics. 2D ferroelectrics offer a new platform for developing ultrathin electronic devices with nonvolatile functionality. Recent experiments on layered α‐In₂Se₃ confirm its room‐temperature out‐of‐plane ferroelectricity under ambient conditions. Here, a nonvolatile memory effect in a hybrid 2D ferroelectric field‐effect transistor (FeFET) made of ultrathin α‐In₂Se₃ and graphene is demonstrated. The resistance of the graphene channel in the FeFET is effectively controllable and retentive due to the electrostatic doping, which stems from the electric polarization of the ferroelectric α‐In₂Se₃. The electronic logic bit can be represented and stored with different orientations of electric dipoles in the top‐gate ferroelectric. The 2D FeFET can be randomly rewritten over more than 10⁵ cycles without losing the nonvolatility. The approach demonstrates a prototype of rewritable nonvolatile memory with ferroelectricity in van der Waals 2D materials.     

The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals

We demonstrate the possibility to control charge trapping in the memory stacks comprised of metal nanocrystals (NCs) sandwiched between SiO₂ and high-k dielectric films by light irradiation. Non-equilibrium depletion effects in the state of the art charge trapping memories are reported for the first time. The studied nonvolatile memory devices employ Au NCs, thermal SiO₂ tunnel layer, atomic layer deposited HfO₂ blocking layer and Au/Pt metal gate. The memory windows are 3 V and 10.5 in the dark and under illumination for ±10 V programming voltages. Reliability limitations of the studied structure, in particular leakage currents and effects in high electric fields have been investigated in detail and are discussed in view of the mentioned device application. Low programming voltages and currents, and high light sensitivity make suggested NVM structures promising for developing digital imagers with ultra-low power consumption.     

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 10³ between the two binary states. Programmed data could be retained for 10³ s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.     

Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory

With the increasing requirement of high density memory technology, a new cell structure—1TR has received much attention. It consists of a single thin film transistor (TFT) with chalcogenide Ge₂Sb₂Te₅ as the channel material. In order to evaluate the feasibility of its application in the field of non-volatile memory, we take a further step in researching on the characteristics of GST-TFT. We fabricated a back-gate GST-TFT and investigated the output and transfer characteristics of its two states. The experimental results show that gate voltage can modulate the GST channel currents in both the amorphous and the crystalline states. Based on the experiments, we can expect that this novel device can ultimately lead to a new nonvolatile memory technology with even higher storage density.     

Two‐ and Three‐Terminal Resistive Switches: Nanometer‐Scale Memristors and Memistors

The logical relationship between two previously defined “memory resistors” is revealed by constructing and experimentally demonstrating a three‐terminal memistor equivalent circuit using two two‐terminal memristors. A technique is then presented, using nanoimprint lithography in combination with angle evaporation, to fabricate a single nanoscale device with a footprint of 4F², where F is the minimum lithographic feature size, that can be operated as either a two‐terminal lateral memristor or a three‐terminal memistor inside a crossbar structure. These devices exhibit repeatable bipolar nonvolatile switching behavior with up to 10³ ON/OFF conductance ratios, as well as the desired three‐terminal behavior.     

Ultraviolet-electrical erasing response characteristics of Ag@SiO2 core-shell functional floating gate organic memory

In the current research of organic memory devices, optimizing the functional layers or introducing appropriate auxiliary operation signals have become two high-profile solutions for device performance optimization. In this work, floating-gate organic memory (FGOM) based on Ag@SiO₂ core-shell nanospheres as the integrated floating gate-tunneling layer are studied. The device with an average thickness of 5 nm silica shell layer exhibits ideal storage characteristics under electrical pulse programming/erasing (P/E) operations. Meanwhile, appropriate incident light with different wavelengths are also applied on the device for optimizing erasing response. The best and reliable nonvolatile memory characteristics are achieved in the one erased by the ultraviolet-assisted electrical pulse, which includes nearly 24 V memory window after 10⁴ s (charge retention rate ≈66%) and nearly 10³ on/off current ratio. By assisting the electrical erasing pulse with the ultraviolet light, a large number of photogenerated carriers can be easily transferred through the thin shell-type tunneling layer and stored. Moreover, the device that only applies the ultraviolet signal to erase also exhibits obvious data discrimination and ideal data retention ability. It stores the optical data while identifying the optical signal, which provides a new realization idea for the integration of ultraviolet light sensor and memory devices.     

Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.     

Air‐Stable Cesium Lead Iodide Perovskite for Ultra‐Low Operating Voltage Resistive Switching

CsPbX₃ (X = halide, Cl, Br, or I) all‐inorganic halide perovskites (IHPs) are regarded as promising functional materials because of their tunable optoelectronic characteristics and superior stability to organic–inorganic hybrid halide perovskites. Herein, nonvolatile resistive switching (RS) memory devices based on all‐inorganic CsPbI₃ perovskite are reported. An air‐stable CsPbI₃ perovskite film with a thickness of only 200 nm is successfully synthesized on a platinum‐coated silicon substrate using low temperature all‐solution process. The RS memory devices of Ag/polymethylmethacrylate (PMMA)/CsPbI₃/Pt/Ti/SiO₂/Si structure exhibit reproducible and reliable bipolar switching characteristics with an ultralow operating voltage (<+0.2 V), high on/off ratio (>10⁶), reversible RS by pulse voltage operation (pulse duration < 1 ms), and multilevel data storage. The mechanical flexibility of the CsPbI₃ perovskite RS memory device on a flexible substrate is also successfully confirmed. With analyzing the influence of phase transition in CsPbI₃ on RS characteristics, a mechanism involving conducting filaments formed by metal cation migration is proposed to explain the RS behavior of the memory device. This study will contribute to the understanding of the intrinsic characteristics of IHPs for low‐voltage resistive switching and demonstrate the huge potential of them for use in low‐power consumption nonvolatile memory devices on next‐generation computing systems.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Organic memory cells based on the switching by nanoparticles containing thin films

We report an electrical bistable switching property in two terminal organic memory cells fabricated with a sandwich structure of Alq₃/Liq/Alq₃, Alq₃/10% doped Liq, and mixed compounds of Alq₃, PVP, and Zn nitrate hexahydrate nanoparticles (NPs) as the active component between two external electrodes. The conductance switching to two states such as ON/OFF states in the ITO/Alq₃/Liq/Alq₃/Al devices shows their conductance difference by ON/OFF ratio of several orders (10³) in magnitude and outstanding stability having a tendency to remain in that states for an extended period of times (∼24 h). Also, the high and low conductivity states of the memory cells can be exactly obtained by applying a negative voltage pulse to write or a positive voltage pulse to erase, respectively. The memory cells have been maintained during numerous (10⁶) writing-erasing cycles in ambient conditions without serious degradation of the device performance.