VLSI局部电源网络的宏模型研究

针对大规模VLSI电源网络分析效率问题,提出一种局部电源网络宏模型求解方法,根据其结构特点,结合电路等效变换与电路合并,对电路模型进行简化,并建立其宏模型.在全局电源网络分析中,利用各局部电源网络宏模型替代其完整电路模型,以降低分析问题的规模与复杂度.实验结果表明,在电源网络分析中应用宏模型技术,可以将分析效率提高1.7倍,且性能随电源网络规模的增大而提高.     

利用Astro-Rail分析FFT芯片的功耗和电源完整性

本文介绍如何使用Synopsys公司的Astro-Rail工具对采用SMIC0.18μmCMOS工艺、已完成布局布线的FFT芯片进行功耗分析、电压降分析和电迁移分析。通过在电压降图和电迁移图中用不同的颜色来显示不同区域的电压降和电迁移情况,可判断出最有可能出现问题的区域。文中利用功耗分析证明了电源和地PAD对的数目符合要求,利用电压降分析和电迁移图证明了电源环和电源条的布置符合工艺要求。     

直线加速器长脉冲调制电源的理论计算

设计并模拟计算了高能直线加速器长脉冲调制电路,该电路所用的储能电容为30μF,由直流高压电源充电到速调管所需工作电压,在1.5ms,800μs和400μs的放电脉宽内,储能电容的电压降分别为5.59%,3.02% 和1.52%,为使负载得到±0.50%的输出脉冲电压,采用补偿电路来补偿脉冲放电期间储能电容的电压降.本文阐述了这种脉冲调制电路的计算结果.     

适于低电源电压应用的新型MOS自举采样开关

提出了一种适合低电源电压应用的新型MOS自举采样开关电路.通过“复制”自举电容和采样开关作为电荷损耗检测电路,并将检测出的电压降低值重新加到自举电容上,解决了传统MOS自举采样开关在低电源电压下工作时的电荷分享问题.基于0.18μm标准CMOS工艺,对电路进行了仿真.结果显示,在输入频率为60 MHz、峰-峰值为1V、采样频率为125 MHz时,与传统自举采样电路相比,新型自举采样电路采样开关管具有更低的导通电阻,无杂散动态范围( SFDR)提高了8dB,特别适合在低压高速A/D转换器中使用.     

基于施密特比较器的高可靠上电复位电路

设计了一款基于施密特比较器的上电复位电路.采用带隙基准源作为施密特比较器的输入参考电压,使电源监控电路具有更加准确的检测电压.给出一个新型结构的延时电路,与传统的RC延时电路相比,在相同的延时下减小了芯片面积.应用数字辅助延时单元,使复位脉冲宽度可控.基于VIS 0.35 μm CMOS工艺,在3.3 V电源电压下进行Cadence Spectre仿真.结果表明,在高电源纹波、上电缓慢、快速掉电/上电等极端情况下,该电路均具有较高的可靠性.     

基于最大电源噪声门级模型的遗传算法电源噪声估计

提出一种能够综合考虑IR drop和di/dt噪声的门级电路模型.实验表明,利用这种模型进行电源噪声估计,可以比传统模型提高5.3%的精度,同时运算时间降低10.7%.根据输入信号对最大电源噪声的影响,还提出了关键输入信号模型.实验表明,在进行电源噪声估计中,基于这些模型的遗传算法,能够比传统的遗传算法提高最多19.0%的精度,并且收敛更加迅速.     

基于最大电源噪声门级模型的遗传算法电源噪声估计

提出一种能够综合考虑IR drop和di/dt噪声的门级电路模型.实验表明,利用这种模型进行电源噪声估计,可以比传统模型提高5.3%的精度,同时运算时间降低10.7%.根据输入信号对最大电源噪声的影响,还提出了关键输入信号模型.实验表明,在进行电源噪声估计中,基于这些模型的遗传算法,能够比传统的遗传算法提高最多19.0%的精度,并且收敛更加迅速.     

基于电流互感的助航灯检测电路寄生电源设计

针对助航灯检测电路的供电问题,研究了从助航灯调光回路寄生取电的方法.助航灯通过电流改变光强等级,鉴于其工作电流范围大的特点,采用基于电流互感器寄生取电方法.建立了互感器取电模型并结合实验得出互感器输出功率与一次侧电流以及负载的关系.根据检测电路功率要求,优化了互感器一次侧设计参数,并采用基于功率电阻的过压保护电路,限定互感器输出电压.实验证明,在助航灯工作在一级至五级光强等级时,电源输出电压稳定,满足检测电路功率要求.     

利用VoltageStorm和APSI工具进行chip-package静态电源分析

目前的片上系统(SoC)设计特点是持续增大的芯片尺寸,集成更多的IP模块,多种电源电压供电,以及封装对供电电压的影响,这加大了不可预测的电压降带来芯片失败的风险。为降低此风险,可使用Cadence公司的SoC电源完整性分析和验证工具VoltageStorm,并结合APSI提取的封装模型,进行chip-package电源完整性分析。本文将结合实际设计项目,介绍利用Cadence公司VoltageStorm和APSI工具进行chip-package电源完整性分析的具体实现。     

基于ARM11的电源完整性分析

为了解决高速多层PCB的电源完整性问题,缩短其开发周期,提高其工作性能,以ARM11核心系统为例,提出利用Cadence PI对PCB进行电源完整性分析的方法.通过对电源系统目标阻抗分析,确定去耦电容的数值,数量以及布局;对电源平面进行直流压降和电流密度分析,改善PCB设计,优化系统的电源完整性.利用动态电子负载搭建的测试平台,对电源仿真分析后制作的PCB进行测试,系统电源完整性较好,表明分析的结果是有效的.     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

A critical analysis of Z-source converters considering the effects of internal resistances

Nowadays Z-source networks are the most promising power converter networks that cover almost all electric power conversion (dc–dc, dc–ac, ac–dc and ac–ac) applications. However, the controller design is critical for Z-source converter (ZSC) due to the presence right-half-plane zero (RHPZ) in the control-to-capacitor-voltage transfer function. This RHPZ exhibits non-minimum phase undershoot in the capacitor voltage and also in the dc-link voltage waveforms. A perfect small-signal model is required to predict locations of the RHP zero and its dynamics. This paper contributes towards the small-signal analysis of ZSC under continuous conduction mode considering the parasitic resistance of the inductor, equivalent series resistance of the capacitor, internal resistances of active switch and forward voltage drop of the diode. The maximum allowable value of shoot-through duty ratio (STDR) and voltage gain for different values of the internal resistance and load resistance are discussed in this paper. The accuracy of the developed small-signal average model is compared with detailed circuit model in MATLAB/SIMULINK. Finally, the steady-state simulation results of ZSC are validated with hardware results.     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

Self-start-up fully integrated DC-DC step-up converter using body biasing technique for energy harvesting applications

An ultra-low power, self-start-up switched-capacitor Two Branch Charge Pump (TBCP) circuit for low power, low voltage, and battery-less implantable applications is proposed. In order to make feasible the low voltage operation, the proposed charge pump along with Non-Overlapped Clock generator (NOC) are designed working in sub-threshold region by using body biasing technique. A four-stage TBCP circuit is implemented with both NMOS and PMOS transistors to provide a direct load flow. This leads to a significant drop in reverse charge sharing and switching loss and accordingly improves pumping efficiency. A post-layout simulation of designed four-stage TBCP has been performed by using an auxiliary body biasing technique. Consequently, a low start-up voltage of 300 mV with a pumping efficiency of 95% for 1 pF load capacitance is achieved. The output voltage can rise up-to 1.88 V within 40 μs with 0.2% output voltage ripple in case of using 400 mV power supply. The designed circuit is implemented by 180-nm standard CMOS technology with an effective chip area of 130.5 μm × 141.8 μm while the whole circuit consumes just 3.2 μW.     

Optimization of via distribution and stacked via in multi-layered P/G networks

The usage of via stack was not carefully studied in previous multi-layered P/G (Power/Ground) network designs. However, with feature size scaling down, the resistance of via is increasing quickly and their influence on voltage drop of P/G networks has become obvious. In this paper, two optimization techniques for via placement are proposed, which are proved to be helpful in reducing on die voltage drop. Firstly, an efficient heuristic algorithm based on sensitivity analysis is presented to optimize via distribution in early design stage. Compared with even distribution design strategies, averagely the heuristic algorithm can reduce the worst voltage drop by 8.43% without adding more vias. Secondly, experiments demonstrated that using stacked vias in nonadjacent layers is powerful in eliminating “hot” areas which suffer from large voltage drop. Based on this observation, a heuristic algorithm is developed to further reduce the worst voltage drop. Experiments show that voltage drop distribution can be well optimized by combining these two strategies together.     

DC-DC低功耗限流电路的设计

设计了一种用于升压型DC-DC转换器的限流电路,可以防止芯片内部的功率开关管遭受大电流的冲击。该电路把电流流过开关管产生的压降与参考电流流过参考管产生的压降相比较,输出电流限制信号,克服了传统限流电路功耗大等缺陷。还设计了一种低功耗的动态参考电流源,其软启动功能能够减小输出电压的过冲。Spectre仿真结果表明,限流电路有效限制了开关管的最大电流,满足设计要求。     

A Low-Loss Built-In Current Sensor

This paper presents a novel built-in current sensor that uses two additional power supply voltages besides the system power supply voltage, and that is constructed by using a current mirror circuit to pick up an abnormal IDDQ. It is activated only by an abnormal quiescent power supply current and minimizes the voltage drop at the terminal of the circuit under test. Simulation results showed that it could detect 16-A IDDQ against 0.03-V voltage drop at 3.3-V VDD and that it reduced performance degradation in the circuit under test. It is therefore suitable for testing low-voltage integrated circuits. Moreover, we verified the behavior of the sensor circuit implemented on the board by using discrete devices. Experimental results showed that the real circuit of the sensor functioned properly.     

Very-low-drop voltage regulator with a fully complementary power process

A very-low-drop voltage regulator is presented that uses an isolated-collector power p-n-p transistor structure to achieve an input-output voltage drop of 0.4 V at 1 A. The device includes a circuit which prevents quiescent current peaks when the p-n-p is in saturation and a Zener-zap trimmed reference makes possible /spl plusmn/1% output voltage tolerance.     

A Wireless Power Interface for Rechargeable Battery Operated Medical Implants

This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm² and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.