一种高精度单环高阶Σ-Δ调制器

设计了一种高精度单环3阶Σ-Δ调制器。阐述了Σ-Δ调制器的结构,确定了前馈因子和增益因子等重要参数。对调制器的各种非理想因素,如时钟抖动、开关非线性、采样电容kT/C噪声等,进行了量化分析和行为级建模。采用MATLAB工具进行了系统验证。验证结果表明,调制器的采样频率为100 kHz,信噪比为99 dB,信噪比最大值为104.2 dB,有效精度达16 位。     

一种低电压3阶4位前馈Σ-Δ调制器

介绍了一种应用于无线通信领域的低电压、带有前馈结构的3阶4位单环Σ-Δ调制器。为了降低Σ-Δ调制器的功耗,跨导放大器采用了带宽展宽技术。采用TSMC 0.13 μm CMOS工艺对电路进行仿真,仿真结果显示,当工作电压为1.2 V、采样频率为64 MHz、过采样比为16、信号带宽为2 MHz时,电路的SNDR达81 dB,功耗仅为7.78 mW。     

低电压Σ-Δ调制器关键技术及设计实例

介绍了低电压开关电容Σ-Δ调制器的实现难点及解决方案,并设计了一种1 V工作电压的Σ-Δ调制器.在0.18 μm CMOS工艺下,该Σ-Δ调制器采样频率为6.25 MHz,过采样比为156,信号带宽为20 kHz;在输入信号为5.149 kHz时,仿真得到Σ-Δ调制器的峰值信号噪声失真比达到102 dB,功耗约为5 mW.     

一种基于动态反相放大器的低功耗Σ-Δ ADC

设计了一种低功耗Σ-Δ ADC。该ADC采用三阶前馈1 bit的结构。为了降低功耗,开关电容积分器的OTA采用动态反相放大器,其具有低功耗、全动态工作、全差分的电路结构、稳定共模点无需CMFB等优点。在SMIC 0.18 μm CMOS工艺下的仿真结果表明,在20 kHz带宽内,4 MHz的采样时钟下,信噪失真比(SNDR)可以达到91.9 dB,动态范围(DR)达到101 dB,有效位数约为15 bit。在1.2 V电源电压下,整体功耗为78 μW。     

斩波稳定型开关电容积分器的设计

利用斩波稳定技术,设计了一种用在Σ-Δ调制器中的低噪声全差分开关电容积分器,电路中的运算放大器采用套筒式共源共栅结构.详细分析了开关电容积分器中存在的非理想特性,同时讨论了斩波稳定的原理,在此基础上对积分器中的运算放大器、开关和电容进行了具体设计.经Cadence环境下的Spectre仿真验证,在3.3 V电源电压下,运算放大器的单位增益带宽为110 MHz,开环直流电压增益达76 dB,积分器在14 kHz处的等效输入噪声电压为0.2 μV·Hz-1/ 2.     

一种高性能多位量化Σ-Δ调制器的设计

实现了一种适用于信号检测的低功耗Σ-Δ调制器。调制器采用2阶3位量化器结构,并使用数据加权平均算法降低多位DAC产生的非线性。调制器采用TSMC 0.18μm混合信号CMOS工艺实现。该调制器工作于1.8V电源电压,在50kHz信号带宽和12.8MHz采样频率下,整体功耗为3mW,整体版图尺寸为1.25mm×1.15mm。后仿真结果显示,在电容随机失配5‰的情况下,该调制器可以达到91.4dB的信噪失真比(SNDR)和93.6dB的动态范围(DR)。     

16位语音Δ-Σ调制器

介绍了一个应用于G.712语音编码的16位2 MHz采样率Δ-Σ调制器(SDM),利用Matlab优化调制器系数,并采用全差分开关电容共模反馈两级跨导放大器和动态比较器降低功耗.模拟结果显示:在2 MHz采样时钟下,输入4 kHz语音信号可获得101 dB信噪比输出,相当于16位精度.电路采用0.18 μm CMOS工艺实现,核心面积为340 μm × 160 μm.电路在1.8 V工作电压和2 MHz采样率下,总功耗约165.6 μW.     

一种高精度离散时间Σ-?调制器的设计

为了满足信号处理的高精度要求，提出了一款信号带宽为1 kHz的三阶一位量化前馈结构的高精度离散时间Σ-?调制器。利用Matlab的SDToolBox工具包分析系统稳定性、计算噪声传递函数并优化系统参数。对电路的非理想因素进行分析及建模仿真，获得子模块的电路参数用于指导晶体管级电路设计。1.8 V电源电压下，基于0.18 μm CMOS工艺设计电路。电路仿真结果表明：输入频率信号频率为375 Hz、采样时钟频率为1.024 MHz时，调制器的信噪比达到133.5 dB，有效位数为21.89 bit。     

16位音频ADC非理想型Σ-Δ调制器的建模

对一款适于16位音频A/D转换器的Σ-Δ A/D调制器进行了系统级设计,考虑了影响调制器性能的各种非理想因素,建立了一整套噪声模型,并进行了仿真分析.将仿真结果与未考虑非理想因素的结果进行比较,可以看出,考虑了非理想因素的建模更能预测实际电路的性能,从而更好地为晶体管级电路设计做铺垫.     

Σ-Δ调制器在非理想环境中的仿真

介绍了一整套Simulink模型,利用其可以对任何Σ-Δ调制器的性能进行详尽的仿真.给出的模型中考虑了大量Σ-Δ调制器的非理想因素,例如采样时钟抖动、kT/C噪声和运算放大器参数(噪声、有限增益、有限带宽、转换速率和饱和电压)等.针对每个模型给出了详尽描述和所有实现细节.文中所有仿真的对象为一典型的二阶SC Σ-Δ调制器结构.最后的仿真结果论证了仿真模型的正确性.     

Continuous time sigma delta ADC design and non-idealities analysis

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS.A detailed non-idealities analysis(excess loop delay,clock jitter,finite gain and GBW,comparator offset and DAC mismatch) is performed developed in Matlab/Simulink.This design is targeted for wide bandwidth applications such as video or wireless base-stations.A third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier -based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency.The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16.The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

一款使用低功耗多级运放实现的12位，20兆带宽，18毫瓦的连续时间型过采样调制器

本文在130纳米CMOS工艺下实现了一种具有20兆赫兹带宽,四阶连续时间型过采样调制器。调制器由有源积分环路滤波器、4位内部量化器和3个电流舵型反馈数模转换器构成。本文提出了一种三级运算放大器,它可以在获得高带内增益和高带宽的同时消耗较小的功耗。为了减小时钟抖动对连续时间型过采样调制器的影响,内部反馈数模转化器采用了不自归零的反馈波形。同时采用特殊的版图技术保证数模转换器的线性度,同时避免使用动态器件匹配技术引入的额外环路延时。芯片工作在1. 2 V 电源电压和480 M Hz 时钟频率, 在20 MHz 的信号带宽内, 调制器的动态范围为66 dB, 峰值SNR为64.6 dB, 功耗为18 mW。     

A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier

正A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth,implemented in 130nm CMOS technology is presented.The modulator is comprised of an active-RC operational-amplifier based loop filter,a 4-bit internal quantizer and three current steering feedback DACs.A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter.Non-return-to -zero DAC pulse shaping is utilized to reduce clock jitter sensitivity.A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy,avoiding the use of a dynamic element matching algorithm to induce excess loop delay.The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio,and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.     

一款调制器和过采样率可配置的单芯片1.2V 95-55dB动态范围的Delta-Sigma模数转换器设计

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.     

一种连续/离散混合结构的音频Sigma Delta模数转换器设计

虽然目前大多数音频ΣΔADC多采用离散时间结构,但是对于需要同时满足高精度、低功耗的新型技术应用,连续时间ΣΔADC的优点越发显得格外明显。连续时间ΣΔADC允许放宽对高增益带宽运算放大器的要求,从而降低了功耗;内置抗混叠滤波器,衰减了带外噪声。本文根据连续时间和离散时间的各自优缺点,提出了一种新型混合结构的四阶、单环、4比特量化ΣΔADC,第一级积分器采用连续时间结构,降低输入噪声、功耗和对输入、反馈驱动电路的需求,第二、三、四级积分器采用离散时间结构,保证了ΣΔADC的线性度和稳定性。测试结果表明混合结构ΣΔADC的峰值信噪比达到100dB,芯片总体功耗为30mW。     

一种采用电容数字自校准技术的连续/离散混合结构Sigma Delta模数转换器设计

虽然目前大多数音频ΣΔADC多采用离散时间结构,但是对于需要同时满足高精度、低功耗的新型技术应用,连续时间ΣΔADC的优点越发显得格外明显。连续时间ΣΔADC允许放宽对高增益带宽运算放大器的要求,从而降低了功耗;内置抗混叠滤波器,衰减了带外噪声。本文根据连续时间和离散时间的各自优缺点,提出了一种采用数字电容自校准技术的连续/离散混合结构的四阶、单环、4比特量化ΣΔADC,电容数字自校准电路用来补偿连续时间积分器的RC常数。测试结果表明混合结构ΣΔADC的峰值信噪比达到102dB,芯片总体功耗为30mW。     

A 102-dB-SNR mixed CT/DT ∑ △ ADC with capacitor digital self-calibration for RC spread compensation

This paper provides a mixed continuous-time/discrete-time,single-loop,4th-order,4-bit audio-band sigma delta ADC with capacitor digital self-calibration for RC spread compensation.This ADC combines the benefits of CT and DT circuits,and the self-calibration control circuits compensate for the variation of the RC product in the continuous-time integrator and for variation in the sampling frequency.Measurement results show that the peak SNR of this ADC reaches 102 dB and the total power consumption is less than 30 mW.     

A continuous-time/discrete-time mixed audio-band sigma delta ADC

This paper introduces a mixed continuous-time/discrete-time,single-loop,fourth-order,4-bit audio-band sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits,while mitigating the challenges associated with continuous-time design.Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.