基于SOI工艺集成电路ESD保护网络分析与设计

由于SOI(Silicon-On-Insulator)工艺采用氧化物进行全介质隔离,而氧化物是热的不良导体,因此SOI ESD器件的散热问题使得SOI电路的ESD保护与设计遇到了新的挑战。阐述了一款基于部分耗尽SOI(PD SOI)工艺的数字信号处理电路(DSP)的ESD设计理念和方法,并且通过ESD测试、TLP分析等方法对其ESD保护网络进行分析,找出ESD网络设计的薄弱环节。通过对ESD器件与保护网络的设计优化,并经流片及实验验证,较大幅度地提高了电路的ESD保护性能。     

0.6μm SOI NMOS器件ESD性能分析及应用

ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...     

集成抗ESD二极管的SOI LIGBT/LDMOS器件结构及其制作方法

为探索与国内VLSI制造工艺兼容的新型SOI LIGBT/LDMOS器件与PIC的设计理论和工艺实现方法，首次提出含有抗ESD二极管的集成SOI LIGBT/LDMOS器件截面结构和版图结构，并根据器件结构给出了阻性负载时器件的大信号等效电路. 探讨了该结构器件的VLSI工艺实现方法，设计了工艺流程. 讨论了设计抗ESD二极管相关参数所需考虑的主要因素，并给出了结构实现的工艺控制要求.     

抗辐照SOI256kB只读存储器的ESD设计

ESD设计技术已成为业界提升SOI电路可靠性的一个瓶颈技术。文章介绍了一款具有抗辐照能力、基于SOI／CMOS工艺技术研制的容量为256kB只读存储器电路的ESD设计方案。结合电路特点详细分析了其ESD设计的难点,阐述了从工艺、器件和电路三个方面如何密切配合,进行SOI电路ESD设计的分析思路和解决方法。电路基于0．8...     

基于130 nm SOI工艺数字ASIC ESD防护设计

绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选.但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点.设计了一款基于130 nm部分耗尽型SOI (PD-SOI)工艺的数字专用IC (ASIC).针对SOI工艺ESD防护设计难点,进行了全芯片ESD防护原理分析,通过对ESD防护器件、I/O管脚ESD防护电路、电源钳位电路和ESD防护网络的优化设计,有效减小了SHE的影响.该电路通过了4.5 kV人体模型ESD测试,相比国内外同类电路有较大提高,可以为深亚微米SOI工艺IC ESD防护设计提供参考.     

部分耗尽SOI ESD保护电路的研究

为了解决SOI技术的ESD问题,我们设计了一种适用于部分耗尽SOI的栅控二极管结构的ESD保护电路,并进行了ESD实验.通过实验研究了SOI顶层硅膜厚度、栅控二极管的沟道长度和沟道宽度,限流电阻以及电火花隙等因素对保护电路抗ESD性能的影响,我们发现综合考虑这些因素,就能够在SOI技术上获得良好的抗ESD性能.     

CMOS/SOI 64-kB SRAM抗ESD实验

设计了一种SOI栅控二极管结构的ESD保护电路，并将其应用到64 kB SRAM电路上，进行了管脚摸底实验和电路的整体抗静电实验。通过实验，研完了ESD保护电路各项参数对ESD性能的影响。实验结果表明，这种结构的ESD保护电路的抗ESD能力达到了设计要求。     

集成抗ESD二极管的SOI LIGBT/LDMOS器件结构及其制作方法

为探索与国内VLSI制造工艺兼容的新型SOI LIGBT/LDMOS器件与PIC的设计理论和工艺实现方法,首次提出含有抗ESD二极管的集成SOI LIGBT/LDMOS器件截面结构和版图结构,并根据器件结构给出了阻性负载时器件的大信号等效电路.探讨了该结构器件的VLSI工艺实现方法,设计了工艺流程.讨论了设计抗ESD二极管相关参数所需考虑的主要因素,并给出了结构实现的工艺控制要求.     

集成抗ESD二极管的SOI LIGBT/LDMOS器件结构及其制作方法

为探索与国内VLSI制造工艺兼容的新型SOI LIGBT/LDMOS器件与PIC的设计理论和工艺实现方法,首次提出含有抗ESD二极管的集成SOI LIGBT/LDMOS器件截面结构和版图结构,并根据器件结构给出了阻性负载时器件的大信号等效电路.探讨了该结构器件的VLSI工艺实现方法,设计了工艺流程.讨论了设计抗ESD二极管相关参数所需考虑的主要因素,并给出了结构实现的工艺控制要求.     

多种栅结构SOI NMOS器件ESD特性研究

研究了不同栅结构对栅接地SOI NMOS器件ESD(Electrostatic discharge,静电放电)特性的影响,结果发现环源结构的SOI NMOS器件抗ESD能力最强,而环栅结构的器件抗ESD能力最弱,其原因可能与器件有缘区面积和电流分布有关。     

SCR-based ESD protection in nanometer SOI technologies

This paper introduces an SCR-based ESD protection design for silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are sometimes better known, have long since been used in Bulk CMOS to provide very area efficient, high performance ESD protection for a wide variety of circuit applications. The special physical properties and design of an SOI technology however, renders straightforward implementation of an SCR in such technologies impossible. This paper discusses these difficulties and presents an approach to construct efficient SCR devices in SOI. These devices outperform MOS-based ESD protection devices by about four times, attaining roughly the same performance as diodes. Experimental data from two 65 nm and one 130 nm SOI technologies is presented to support this.     

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.     

ESD reliability and protection schemes in SOI CMOS output buffers

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<>     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI nMOSFET's that can be exploited to clamp HBM ESD stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.     

Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices

Triggering uniformity and current sharing under TLP stress is investigated in low voltage multi-finger gg-NMOS and NPN ESD protection devices fabricated in smart-power SOI technology. Inhomogeneous current distribution over the fingers and within a single finger is detected by the backside transient interferometric mapping (TIM) technique. 2D TCAD device simulations of the multi-finger devices are used to explain the experimental TIM results. Changes in differential resistance in the pulsed IV characteristics of the NPN ESD protection devices are also explained by TIM experiments.     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。