A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

Order selection statistical test for nonstationary AR models

A new statistical test for selecting the order of a nonstationary AR modelyk is presented based on the predictive least-squares principle. This test is of the same order as the accumulated cost function _n = _k=1 ⁿ ( _k ^* – _k )²;i.e., ^* wherey _k ^* is the predictive least-square estimate. It is constructed to show how many times the integrated AR processy _k is differenced in order to obtain a stationary AR process given that the exact order of the process is unknown.     

Differential fault simulation for sequential circuits

A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of C language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.     

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log₂ n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.Supported by C&C Research Laboratories, NEC USA, during summer 1991.     

On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming

Many important algorithms can be described by n-dimensional uniform recurrences. The computations are then indexed by integral vectors of length n and the data dependencies between computations can be described by the difference vector of the corresponding indexes which are independent of the indexes. This paper addresses the following optimization problem: Given an n-dimensional uniform recurrence whose computation indexes are mapped by a linear function onto the processors of an array processor embedded in k-space (1 k n). Find an optimal linear function for the computation indexes. We study a continuous approximation of this problem by passing from linear to quasi-linear timing functions. The resultant problem formulation is then a quadratic programming problem which can be solved by standard algorithms for quadratic or general nonlinear optimization problems. We demonstrate the effectiveness of our approach by several nontrivial test examples.     

Fast correlation attacks on certain stream ciphers

Suppose that the output of a running key generator employed in a stream cipher is correlated to a linear feedback shift register sequence (LFSR sequence) a with correlation probabilityp>0.5. Then two new correlation attacks (Algorithms A and B) are presented to determine the initial digits of a, provided that the numbert of feedback taps is small (t<10 ifp0.75). The computational complexity of Algorithm A is of orderO(2^ck), wherek denotes the length of the LFSR andc<1 depends on the input parameters of the attack, and Algorithm B is polynomial (in fact, even linear) in the lengthk of the LFSR. These algorithms are much faster than an exhaustive search over all phases of the LFSR, and are demonstrated to be successful against shift registers of considerable lengthk (typically,k=1000). On the other hand, for correlation probabilitiesp0.75 the attacks are proven to be infeasible against long LFSRs if they have a greater number of taps (roughlyk100 andt10).This work was supported in part by GRETAG Ltd., Regensdorf, Switzerland.     

Fault Models and Test Generation for OpAmp Circuits—The FFM

The analog VLSI technology processes are reaching the matureness, nevertheless, there is a big constraint, regarding their use on complex electronic products: the test. The Design for Testability paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The results have shown that high level OpAmp requirements, as slew-rate, common mode rejection ration etc., can be checked by this approach with good compromise between the fault modeling problem, the analog nature of the circuit and the circuit complexity by itself.     

Input-Free V TP and - V TN Extractor Circuits Realized on the Same Chip

The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, V _TP and -V _TN . Both outputs are referenced to the same V _DD supply line, and hence, the circuit can be used as a convenient test device. The V _TP extractor is based on the nested connection of two transistors; the -V _TN extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The circuit was realized in 0.8 m technology, and the results of simulation and experiment are compared. Recommendations to improve the design are given.     

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.     

Fault diagnosis under a limited-fault assumption and limited test-point availability

This paper describes a method of fault diagnosis for large interconnected circuits in which the number of faults is limited to, say,n _f where it is possible thatn _f exceeds the number of output measurements,n _o. The problem and its solution are formulated in the context of a frequency domain tableau based on the component connection model of a circuit/system. The paper describes Jacobian tests for diagnosability whenn _fn _o and states a full parameter diagnosability test as a corollary to the main theorem. An algorithm is developed for the identification of faulty parameters in this limited fault case. Finally, examples, including a 26-parameter video-amplifier circuit, illustrating the technique are given.     

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults

This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 2^2k , 1k[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.This work was supported in part by Reserach Grants No. 5711 and No. 39409 and a Strategic Grant from the Natural Sciences and Engineering Research Council of Canada and by an equipments loan from the Canadian Microelectronics Corporation.A preliminary version of this paper is partially presented at theIEEE ISCAS'94, May 1994.     

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation represents an upper limit of what is possible from any type of model, but that good parameter extraction is required to most closely approach that limit. The individual model types presently in common use are examined, with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of circuits, and criteria that a circuit design consumer can employ to judge a model before using it for circuit design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of MOSFET modeling for circuit simulation are considered.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

An On-Chip BP Learning Neural Network with Ideal Neuron Characteristics and Learning Rate Adaptation

An on-chip BP(Back-Propagation) learning neural network with ideal neuron characteristics and learning rate adaptation is designed. A prototype LSI has been fabricated with a 1.2 m CMOS double-poly double-metal technology. A novel neuron circuit with ideal characteristics and programmable parameters is proposed. It can generate not only the sigmoid function but also its derivative. The test results of this neuron circuit show that both functions match with their ideal values very accurately. A learning rate adaptation circuit is also presented to accelerate the convergence speed. The 2-D binary classification and sin(x) function fitness experiments are done to the chip. Both experiments verify the superior performance of this BP neural network with on-chip learning.     

A canonical form for discrete-time systems defined overZ + *

It is shown that for each memberG of a large class of causal time invariant nonlinear input-output maps, with inputs and outputs defined on the nonnegative integers, there is a functionalA on the input set such that (Gs)(k) has the representationA(F _k s) for allk and each inputs, in whichF _k is a simple linear map that does not depend onG. More specifically, this holds—with anA that is unique in a certain important sense—for anyG that has approximately finite memory and meets a certain often-satisfied additional condition. Similar results are given for a corresponding continuous-time case in which inputs and outputs are defined on ₊. An example shows that the members of a large family of feedback systems have these A-map representations.     

Pure mode versus mixed mode interfacing between analog circuits

The concepts of transmission error and mismatch factor ^–1 are introduced to evaluate the effect of impedance mismatch on the accuracy of broadband signal transmission between two feedback amplifiers. It is shown that, in comparison with the error introduced by the feedback amplifiers, becomes negligible for pure V.M. (voltage mode) or C.M. (current mode) signal transmission; in the mixed mode, in which a V.M. output circuit feeds a C.M. input circuit, or vice versa, may become significant. Computer simulations show that the pure mode also yields reduced T.H.D., improved bandwidth and improved transient response. It is also shown that a particular combination between the kind of feedback and the active circuit to which it is applied, termed enhancing combination, further increases the accuracy of signal transmission.1. The notation (OL) relates to the open-loop value of the parameter involved.2. It can be shown that rule 2 does not apply to a low-noise preamplifier.     

Generating nonorthogonal bases for signal representation

The representation of functions in a basis function expansionz(t)= k=1/=,a _k> x _k (t) is straightforward when the basis functionsx _k (t) are orthogonal. There has been very little work up to this time in determining how to use nonorthogonal bases in signal representation. On the other hand, applications in data compression and signal synthesis often require using specific tailor-made bases. Presented here is a method for constructing very general nonorthogonal bases.Orthogonality has often been used to show that a basis spans the set of functions of interest and to calculate the coefficients of the representation. In this paper, both of these fundamental aspects are addressed for nonorthogonal bases. A new basis {y _k (t)} is obtained by performing a linear transformation on a known existing basis {x _k (t)}. This transformation is constructed such that the coefficients of signal representation on the new basis are readily found. Then, a useful and sufficient condition is placed upon the new basis such that representations converge.The fundamental methods are applied to the standard examples of signal representation. The complex sinusoids, the Rademacher functions, the orthogonal polynomials, and the decaying exponentials are used as the original basis {x _k (t)} from which a new basis {y _k (t)} is generated. Two examples are given to illustrate general applications: one in signal synthesis and one in signal analysis.     

Geometric properties of nonlinear networks containing capacitor-only cutsets and/or inductor-only loops. Part I: Conservation laws

This paper is the first in a two part sequence which studies nonlinear networks, containing capacitor-only cutsets and/or inductor-only loops from the geometric coordinate-free point of view of differentiable manifolds. Given such a nonlinear networkN, with °₀ equal to the sum of the number of independent capacitor-only cutsets and the number of independent inductor-only loops, we establish the following: (i) circuit theoretic sufficient conditions to guarantee that the set ⁰, of equilibrium points is a ₀-dimensional submanifold of the state space ofN; (ii) circuit theoretic sufficient conditions for the condition thatN has ₀ independent conservation laws and hence that through each point of the state space ofN, there passes a codimension ₀ invariant submanifold ^* of the network dynamics; (iii) circuit theoretic sufficient conditions to guarantee that the manifolds ^* and ⁰ intersect transversely.This work was supported by the Natural Sciences and Engineering Research Council of Canada, under Grant Number A7113, and by scholarships from the Natural Sciences and Engineering Research Council of Canada and the Ontario Provincial Government.     

一种可逆有限状态机的电路设计

不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.