共查询到20条相似文献,搜索用时 125 毫秒
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AD1380是美国模拟器件公司推出的16位并行或串行输出的模/数转换器.本文简单介绍AD1380的技术性能及与8031单片机接口中应注意的问题. 相似文献
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基于CAN总线的智能型温湿度采集系统设计 总被引:3,自引:1,他引:2
设计一种基于CAN总线的智能型温湿度数据在线采集系统。该系统主要由两大模块构成:现场数据采集模块和USB~CAN转换接口模块。现场数据的采集是以AT89S52单片机为核心控制单元,外接温度传感器AD590和湿度传感器HM1500,通过CAN总线控制器SJA1000将数据发送到CAN总线上;USB—CAN转换接口模块是以ATmega 162芯片为控制单元,外接FT245BM USB通信芯片及SJA1000控制器,实现USB—CAN接口转换。整个系统的终端设备为监控PC机,用户软件采用VC^++语言编写,可以实现现场状态监控、上下限报警和中断接收数据管理等功能。 相似文献
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《Solid-State Circuits, IEEE Journal of》1978,13(6):746-753
The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the converter appears as a memory location to the microprocessor. It can be programmed to operate in a wide variety of modes and can interface with the fastest MOS and TTL microprocessors. The converter offers high-speed multiplying operation and an output current mode multiplexer. Status latches are provided to store multiplexer and code select commands. Nonsaturating multilevel logic operating nearly in the linear region provides gate delays of less than 5 ns when fabricated on the same chip with precision linear functions. 相似文献
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《Solid-State Circuits, IEEE Journal of》1983,18(6):745-753
A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible. 相似文献
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星载电子设备多余物数据采集系统的设计 总被引:1,自引:0,他引:1
为实现尺寸较大、内部结构较为复杂的星载电子设备的多余物自动检测,设计了以EZ-USB FX2和CPLD芯片为核心器件的数据采集卡,实现了四通道的同步数据采集和传输。此系统包括数据采集、数据缓存以及数据控制和传输,分别采用了采样率为500 k的12位A/D转换器件AD7892、16 k×18位的FIFO CY7C4265、EPM7064和USB芯片CY7C68013。重点介绍了数据采集系统的硬件组成和软件设计,包括USB的固件程序、CPLD的控制程序和主机用户程序。实验结果表明,该系统能达到稳定传输速度为15.4 MB/s,保证了四通道同时以500 k的采样率工作的稳定性和正确性。 相似文献
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为方便地获得多路小电流的温度信号,设计了基于USB2.0的16通道数据采集系统。讨论了基于USB采集系统的设计,包括系统的硬件和软件程序设计。其中系统硬件采用USB2.0接口芯片CY7C68013和具有电流电压转换功能的A/D芯片DDC316实现小电流数据的采集、传输;软件设计部分包括系统的固件程序、驱动程序、用户的应用程序3部分。数据采集系统具有最大20ks/s的采样速率,16位分辨率,采样精度小于1%,系统满足设计需求,具有高性能、低成本的特点,可广泛应用于信号分析、测控等多个领域。 相似文献
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《Solid-State Circuits, IEEE Journal of》1983,18(3):297-301
A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip. The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal. The small chip size of about 8.5 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution control loop systems. A modified test chip is also described which has been provided as a step into the field of accurate monolithic converters needed for digital audio systems. A voltage output settling time less than 10 /spl mu/s and a linearity at the 12 bit level have been achieved. 相似文献
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A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply. 相似文献