Test structures to measure the Seebeck coefficient of CMOS ICpolysilicon

We report on two thermal characterization structures to measure the Seebeck coefficient α of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 μm CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent α of the two polysilicon layers of the AMS process was measured with both devices. The agreement between the thermoelectric coefficients obtained with the two types of structures is better than 2.1 μV at 300 K     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

Improving the activation of the P/sup +/ region of low-temperature polycrystalline Si TFTs by using solid-phase Crystallization

We have developed a low-temperature fabrication process for making thin-film transistors (TFTs) with highly activated source and drain regions by utilizing pre-amorphization by Ge-ion implantation followed by solid-phase crystallization. The sheet resistances of the p/sup +/ polysilicon layers formed by B-ion implantation with and without Ge-ion implantation were, respectively, 200 and 1500 /spl Omega//sq. We confirmed reducing the sheet resistance of p/sup +/ polysilicon increases the on-current of TFTs on glass substrates. This process is promising for making high-performance CMOS peripheral circuits for liquid crystal display panels.     

CMOS工艺兼容多晶硅压力敏感膜的设计与加工

在MEMS表面加工工艺中 ,多晶硅薄膜是微结构的重要组成部分。本文考虑加工工艺中残余应力的影响和多晶硅材料的强度范围 ,建立多晶硅膜的大变形模型 ,设计可用于压力传感器应用的多晶硅薄膜几何尺寸。采用有限元方法对多晶硅薄膜进行力学分析和设计验证 ,提出了CMOS工艺兼容的多晶硅压力敏感膜的加工方法 ,并且根据所设计的工艺进行了电容式压力传感器微结构的加工 ,加工结果说明了多晶硅薄膜设计的合理性和CMOS兼容工艺的可行性     

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.     

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented.<>     

用发光显微镜测试控制先进CMOS工艺的多晶硅刻蚀时间

通过结合发光显微镜(EMMI)测试和poly-edge电容测试结构很好地控制了多晶硅刻蚀时间,避免了栅极氧化膜的早期失效.从栅极氧化膜击穿电压的测试结果可以看出,当刻蚀时间较短时,一个晶圆内几乎所有测试结构都呈现早期失效模式.通过延长刻蚀时间,早期失效数逐渐减少,最后可以完全消除早期失效,所有测试结构都为本征失效.为了分析多晶硅刻蚀时间和氧化膜失效模式的关系,对早期失效和本征失效样品进行了发光显微镜测试.Poly-edge电容结构的测试结果表明,过短的刻蚀时间导致了多晶硅在STI沟槽中的残留,硅化工艺后,这些多晶硅会使栅极和衬底短路,从而导致了栅极氧化膜的早期失效.通过延长刻蚀时间,可以有效地清除多晶硅的残留,从而保证栅极氧化膜的可靠性.     

用发光显微镜测试控制先进CMOS工艺的多晶硅刻蚀时间

通过结合发光显微镜(EMMI)测试和poly-edge电容测试结构很好地控制了多晶硅刻蚀时间,避免了栅极氧化膜的早期失效.从栅极氧化膜击穿电压的测试结果可以看出,当刻蚀时间较短时,一个晶圆内几乎所有测试结构都呈现早期失效模式.通过延长刻蚀时间,早期失效数逐渐减少,最后可以完全消除早期失效,所有测试结构都为本征失效.为了分析多晶硅刻蚀时间和氧化膜失效模式的关系,对早期失效和本征失效样品进行了发光显微镜测试.Poly-edge电容结构的测试结果表明,过短的刻蚀时间导致了多晶硅在STI沟槽中的残留,硅化工艺后,这些多晶硅会使栅极和衬底短路,从而导致了栅极氧化膜的早期失效.通过延长刻蚀时间,可以有效地清除多晶硅的残留,从而保证栅极氧化膜的可靠性.     

Calculation of the current response of the spatially modulatedlight CMOS detector

We present an analytical model that allows to calculate the current response of a spatially modulated light CMOS detector (SML-detector) and compare this response with the response of a traditional CMOS photodetector. It is shown that the SML detector already yields a three orders of magnitude faster response time than a traditional CMOS detector in a 0.25 μm CMOS technology. This response time will further decrease as CMOS technology evolves. This analytical expression is compared with a numerical solution of the diffusion equation and with experimental results. Both show an excellent correspondence. Therefore we can conclude that the SML-detector is the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems     

Nitrogen implanted polysilicon resistor for high-voltage CMOStechnology application

A nitrogen-implanted polysilicon thin film resistor has been proposed to improve the electrical characteristics of resistors in high-voltage CMOS technologies. The SIMS profile shows the proposed nitrogen-implanted polysilicon resistor can raise 100 times of the concentration of nitrogen. Thereby, the temperature coefficient of resistance (TCR), voltage coefficient of resistance (VCR), and mismatch are improved 20.4%, 35.9%, and 23.5% in average, respectively. The improvements are attributed to the suppression of both hydrogen intrusion by the presence of high-nitrogen concentration in polysilicon     

A transistor performance figure-of-merit including the effect ofgate resistance and its application to scaling to sub-0.25-μm CMOSlogic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness     

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

Overlaid CMOS

A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.     

Bias temperature instability assessment of n- and p-channel MOS transistors using a polysilicon resistive heated scribe lane test structure

A fast wafer level device reliability stress at elevated temperatures is demonstrated. It neither needs an external heat source like a thermal chuck or an oven nor cooling. The necessary temperature for acceleration of the bias temperature stress drift mechanism is achieved by electrically resistive heating. For this reason a polycrystalline silicon (polysilicon) resistive heated test structure was designed with a MOSFET embedded between two polysilicon heater strips. A 4-terminal metal resistor above the heater allows temperature control via the temperature coefficient of the resistance. The stress algorithm performs simultaneous thermal and electrical stress. The device temperature is determined by a comparison of the temperature measured at the metal level and the pn-junction temperature determined from the forward diode characteristics. Results of an assessment of the bias temperature instability of CMOS transistors using this type of structure are discussed. They demonstrate the usefulness of the whole methodology presented.     

A Compact Model for Polysilicon TFTs Leakage Current Including the Poole–Frenkel Effect

Based on a generation-recombination model including the Poole-Frenkel (PF) effect and phonon-assisted tunneling, numerical analysis shows that the logarithm of generation rate for polysilicon thin-film transistors (poly-Si TFTs) working in the leakage region is linear with the square root of lower electric field and approximately linear with higher electric field over a wide temperature range (273-423 K). Therefore, an analytical expression is found to approximate the generation rate. Furthermore, a compact model for poly-Si TFT leakage current including the PF effect is developed in this paper. The proposed model is analytical without numerical calculation, and its parameters can be extracted from experimental data; hence, it is attractive for circuit simulation. The model has been verified by comparing simulated results with experimental data.     

A high-performance directly insertable self-alignedultra-radiation-hard and enhanced isolation field-oxide technology forgigahertz Si-CMOS VLSI

A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10⁸ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad     

On the resistivity of TiSi2: The implication for low-temperature applications

The electrical resistivity of TiSi2formed on polysilicon implanted with phosphorus and arsenic and on n⁺and p⁺diffusions implanted with arsenic and boron was measured in the 4.2-300 K temperature range. It is found that in all cases, the resistivity is reduced by a factor of 3-4 when TiSi2is cooled from room to liquid-nitrogen temperature. Sheet resistance as low as 1 Ω/sq. at liquid-nitrogen temperature can be easily achieved for self-aligned thin TiSi2layers over polysilicon and diffusion regions, which is very attractive for low-temperature CMOS applications. The residual resistivity ratio, which is a measure of the electron mean free path, decreases with growing surface concentration of dopants, regardless of doping species. The analysis of thickness effects in terms of surface scattering and of grain boundary resistivity models, suggests that degradation of sheet resistance Rswith increased implantation dose is due only partly to the difficulty in forming thick enough TiSi2at high doses, and that dopant impurities segregated at the grain boundaries can account for the observed increase.     

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at V/sub DS/=1 V) and a drain-induced barrier lowering of 0.12 V.