AlGaN/GaN高电子迁移率晶体管的可靠性

利用正向肖特基结结电压与温度的线性关系,对AlGaN/GaN HEMT器件有源区瞬态温升进行了测量,其热阻为19.6℃/W。比较了不同测温方法和外界环境对器件沟道温升的影响。并研究了栅极施加反向直流阶梯应力对AlGaN/GaN HEMT器件性能的影响,结果表明器件在应力作用下电学参数退化,大信号寄生源/漏极电阻RS/RD和栅源正向I-V特性在击穿后能得到恢复。AlGaN势垒层陷阱俘获电子和电子填充栅极表面态是器件参数退化的原因,表面态恢复是器件参数恢复的主要原因。     

增强型AlGaN/GaN/AlGaN双异质结槽栅HEMT研究

为了在获得高击穿电压的同时实现增强型器件,对AlGaN/GaN/AlGaN双异质结HEMT进行了栅槽刻蚀,得到阈值电压为0.6 V的增强型HEMT。对器件特性的变化机理进行了分析,发现刻蚀引入的陷阱态使器件的击穿性能降低。采用变频电导法,定量研究了反应离子刻蚀在AlGaN/GaN/AlGaN双异质结HEMT中引入的陷阱态。研究表明,刻蚀工艺在双异质结HEMT中引入了大量的浅能级陷阱,这些陷阱的能级主要分布在0.36~0.40 eV。     

AlN阻挡层对AlGaN/GaNHEMT器件的影响

利用低压MOCVD技术在蓝宝石衬底上生长了AlGaN/GaN异质结和AlGaN/AlN/GaN异质结二维电子气材料,采用相同器件工艺制造出了AlGaN/GaN HEMT器件和AlGaN/AlN/GaN HEMT器件.通过对两种不同器件的比较和讨论,研究了AlN阻挡层的增加对AlGaN/GaN HEMT器件性能的影响.     

AlN阻挡层对AlGaN/GaN HEMT器件的影响

利用低压MOCVD技术在蓝宝石衬底上生长了AlGaN/GaN异质结和AlGaN/AlN/GaN异质结二维电子气材料,采用相同器件工艺制造出了AlGaN/GaN HEMT器件和AlGaN/AlN/GaN HEMT器件.通过对两种不同器件的比较和讨论,研究了AlN阻挡层的增加对AlGaN/GaN HEMT器件性能的影响.     

UV/Ozone 表面处理对AlGaN/GaN HEMTs 性能的影响

工艺过程中对晶圆表面处理对制作出高性能的AlGaN/GaN HEMT起到至关重要的作用,洁净的表面能够有效提高器件性能以及器件可靠性。本文发现通过UV/Ozone表面处理,AlGaN/GaN HEMT器件的欧姆接触以及肖特基接触的电学特性均发生明显变化,根据实验中现象以及相关实验数据,并且采用X射线光电子能谱对实验样品进行表面分析测试,着重阐述了UV/Ozone处理对晶圆表面的作用,以及其影响AlGaN/GaN HEMT器件欧姆接触特性以及肖特基接触特性的原因。     

GaN基HEMT器件的优化设计北大核心CSCD

针对氮化镓(GaN)高电子迁移率晶体管(HEMT)器件自热效应以及电流崩塌效应导致器件性能退化和失效的问题,研究了通过合理改变器件参数尺寸优化GaN基HEMT器件的设计,提高器件性能。通过仿真软件模拟了器件各参数对于GaN器件电学性能的影响,分析了不同衬底构成对GaN HEMT器件自热效应的影响,系统研究了GaN HEMT器件相关参数改变对自热效应及器件电学性能的影响。结果表明:Si及金刚石组成的衬底中减小Si层的厚度有利于减小器件的自热效应,降低有源区最高温度。为提高器件性能以及进一步优化GaN基HEMT器件设计提供了一定的理论参考。     

GaN基HEMT器件的优化设计

针对氮化镓(GaN)高电子迁移率晶体管(HEMT)器件自热效应以及电流崩塌效应导致器件性能退化和失效的问题,研究了通过合理改变器件参数尺寸优化GaN基HEMT器件的设计,提高器件性能。通过仿真软件模拟了器件各参数对于GaN器件电学性能的影响,分析了不同衬底构成对GaN HEMT器件自热效应的影响,系统研究了GaN HEMT器件相关参数改变对自热效应及器件电学性能的影响。结果表明:Si及金刚石组成的衬底中减小Si层的厚度有利于减小器件的自热效应,降低有源区最高温度。为提高器件性能以及进一步优化GaN基HEMT器件设计提供了一定的理论参考。     

GaN HEMT器件60Co-γ辐照效应研究

研究了总剂量4 Mrad(Si) ⁶⁰Co-γ辐照对AlGaN/GaN HEMT器件的影响，器件在辐照过程中采用不同的加电方式。辐照过程会增加器件的栅泄漏电流，但辐照终止后电流快速恢复至初始状态。对比辐照前后的直流性能，器件的肖特基势垒高度、阈值电压、漏电流、跨导等未出现退化问题。实验结果表明，基于自主开发的GaN标准工艺平台所制备AlGaN/GaN HEMT器件，具有稳定可靠的⁶⁰Co-γ抗辐照能力。     

AlGaN/GaN HEMT的恒压电应力退化研究

研究了AlGaN/GaN高电子迁移率晶体管(HEMT)在不同持续恒压电应力条件下的退化机制,制作了一种AlGaN/GaN HEMT。对该器件分别采用恒压开态应力和恒压关态应力,研究了与直流特性相关的重要参数的陷阱产生规律。实验结果表明,在开态应力下,由于存在热载流子效应,发生了阈值电压正漂现象,峰值跨导降低;在关态应力下,由于存在逆压电效应,发生了阈值电压负向漂移现象。     

GaN基HEMT器件抗逆压电性能研究

可靠性问题是GaN基HEMT器件走向实用化的关键,逆压电效应导致器件退化是近年来比较引人瞩目的理论之一。对于GaN基HEMT器件,当其承受外加电场时,由于逆压电效应,电场最终转化成弹性势能。当电场足够大,突破势垒层材料所能承受的临界弹性势能,势垒层材料就会发生松弛。根据逆压电效应导致器件退化机理,从弹性势能的角度出发,对低Al组分AlGaN势垒层、InAlN势垒层和AlGaN背势垒等三种结构进行理论分析。分析表明,三种结构均能较大程度地改善GaN基HEMT器件的抗逆压电能力,从而提高器件可靠性。     

GaN HFET的性能退化

在综述大功率AlGaN/GaN HFET性能退化实验结果的基础上,研究了器件退化与电流崩塌间的关联。分析了现有各类器件失效模型的优点和不足之处。通过沟道中强电场和热电子分布的研究,完善了热电子触发产生缺陷陷阱的器件退化模型。使用这一模型解释了实验中观察到的各类性能退化现象,指出优化设计异质结构可以有效减弱GaN HFET的性能退化。最后提出减弱器件性能退化的方法和途径。     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs

In the present paper, an accurate surface potential and the subthreshold swing (S) models including the free carriers and interfacial traps effect have been presented. Exploiting these new device models, we have found that the incorporation of the free carriers' effect leads to the improvement of the subthreshold swing accuracy in comparison with the classical models. The inclusion of the free carriers has a major role in determining the subthreshold parameters behavior due to the extra surface potential generated at the interface, which may affect the electric field and carriers transport in weak inversion regime. We have demonstrated that S is very sensitive to the short channel lengths (L less than 40 nm). For a device with a small silicon body thickness (t_si=5 nm), S is increased dramatically with the reduction of the channel length. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for a wide range of device parameters and bias conditions. The proposed models can also be implemented into devices simulators, such as SPICE, to study the degradation of nanoscale digital CMOS-based circuits.     

Identifying the spatial position and properties of traps in GaN HEMTs using current transient spectroscopy

Time constant spectra are extracted from current transients based on the Bayesian deconvolution and used to characterize traps in GaN high-electron mobility transistors. Two kinds of traps with different time constants in an actual device were identified in the AlGaN barrier layer and the GaN layer, respectively. In particular, the trapping process in the AlGaN barrier layer was identified at the region near the drain side under gate contact. Trapping mechanisms of both two traps are discussed. Additionally, we observe that the trap in the AlGaN barrier layer requires sufficient electric field to activate the trapping process and a high drain voltage (V_ds) accelerates the trapping processes both in the AlGaN barrier layer and the GaN layer. In addition, detrapping experiments with different filling conditions were performed to confirm their spatial positions. The influence of self-heating is excluded during the experiment by keeping the power density at a very low level, and the trapping effect is the sole factor accounting for the current transients.     

Localized interface trap generation in SILO-isolated MOSFETs duringPECVD nitride passivation

The authors report the generation of interface traps during the plasma-enhanced chemical vapor deposition of silicon nitride passivation in MOS structures that utilize a sealed-interface local oxidation scheme (SILO) for device isolation. These traps are highly localized at the boundaries between gate and field oxides, causing enhanced subthreshold conduction. Localized interface traps of this type were not observed in identical MOS structures that use conventional LOCOS (local oxidation of silicon) isolation and were eliminated by thermal anneals at 450°C. Anneals in hydrogen ambients resulted in enhanced rates of hot-carrier-induced degradation. The high densities and localized nature of these anomalous traps make possible a novel mode of device operation in which source-drain conduction is strongly modulated by substrate bias     

Lateral distribution of hot-carrier-induced interface traps inMOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also     

A comprehensive study of hot-carrier induced interface and oxidetrap distributions in MOSFETs using a novel charge pumpingtechnique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N_it) and oxide (N_0t) traps in hot-carrier stressed MOSFETs. Direct separation of N_it and N_0t is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms     

Radiation damage and its effect on hot-carrier induced instability of 0.5 μm CMOS devices patterned using synchrotron x-ray lithography

The device characteristics and the radiation damgae ofn-channel andp-channel MOSFETs patterned using synchrotron x-ray lithography are examined. The effect of radiation damage caused by x-ray lithography on the device reliability during hot electron injection is investigated. In addition to neutral traps, large amounts of positive oxide charge and interface states, particularly acceptor-like interface states, which cause degradation of MOSFET characteristics are found to be created by x-ray irradiation during the lithography process. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron induced instability inp-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. The effect of radiation damage on hot electron induced instability is found to be more severe inn ⁺-poly buried-channelp-MOSFETs than inp ⁺-poly surface-channel p-MOSFETs. However, the degradation inn-channel MOSFETs due to channel hot carriers is not significantly increased by x-ray lithography. These results suggest that the major degradation mechanism due to hot-carrier inp-channel MOSFETs is electron trapping and inn-channel MOSFETs is interface state generation. It also suggests thatp-channel MOSFETs, in addition ton-channel MOSFETs, needs to be carefully examined in terms of hot carrier induced instability in CMOS VLSI circuits patterned using x-ray lithography.     

雪崩光电探测器的击穿效应模型分析

基于CMOS工艺制备了空穴触发的Si基雪崩探测器(APD),基于不同工作温度下器件的击穿特性,建立空穴触发的雪崩器件的击穿效应模型。根据雪崩击穿模型和击穿电压测试结果,拟合曲线得到击穿电场与温度的关系参数(dE/dT),器件在250～320 K区间内,击穿电压与温度是正温度系数,器件发生雪崩击穿为主,dV/dT=23.3 mV/K,其值是由倍增区宽度以及载流子碰撞电离系数决定的。在50～140 K工作温度下,击穿电压是负温度系数,器件发生隧道击穿,dV/dT=-58.2 mV/K,其值主要受雪崩区电场的空间延伸和峰值电场两方面因素的影响。     

Characteristics degradation of the SiGe HBT under electromagnetic field stress

This paper describes a new reliability study in SiGe Heterojunction Bipolar Transistors (HBTs) by which the electromagnetic field aggression effects can be identified. Base current deviation mechanism with current gain degradation is studied for the first time. Reverse Gummel plots and capacitance characterizations indicate that the electromagnetic field stress induces traps not only at the emitter–base spacer’s oxide, but also at the collector–base spacer’s oxide. These traps induce generation/recombination centers, and leads to excess non-ideal base currents. Two-dimensional physical simulations have been used to analyse the impact of this degradation mechanism on the device behavior. As a consequence of introducing surface recombination centers at emitter–base and collector–base spacer’s oxide, a non-ideal base current rises up in agreement with the experimental data extracted. As the density of interface traps increases, the charge contributed by these interface states causes a broadening in the base current response and the capacitances deviation.