共查询到18条相似文献,搜索用时 109 毫秒
1.
制造工艺的不断进步,嵌入式存储器在片上系统芯片中的集成度越来越大,同时存储器本身也变得愈加复杂,使得存储器出现了一系列新的故障类型,比如三单元耦合故障.存储器內建自测试技术是当今存储器测试的主流方法,研究高效率的Mbist算法,是提高芯片成品率的必要前提.以SRAM的7种三单元耦合故障为研究对象,通过分析故障行为得到三单元耦合的72种故障原语,并且分析了地址字内耦合故障的行为,进而提出新的测试算法March 3CL.以2048X32的SRAM为待测存储器,利用EDA工具进行了算法的仿真,仿真结果表明,该算法具有故障覆盖率高、时间复杂度低等优点. 相似文献
2.
一款雷达信号处理SOC芯片的存储器内建自测试设计 总被引:2,自引:1,他引:1
内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障. 相似文献
3.
4.
基于March算法的存储器内建自测试电路能够获得很高的故障覆盖率,但在测试小规模的存储器时暴露出了面积相对比较大的缺点.针对大屏幕Timing Controller芯片"龙腾TC1"中4块640×18 bit SRAM"按地址递增顺序连续进行写操作"的工作特点,提出了一种新的存储器内建自测试方法.该方法按照地址递增顺序向存储器施加测试矢量,避免了直接采用March C算法所带来的冗余测试,简化了内建自测试电路,大大减少了由管子的数量和布线带来的面积开销,可达到March C 算法相同的"测试效果". 相似文献
5.
6.
LSC87中嵌入式ROM内建自测试实现 总被引:2,自引:1,他引:1
LSC87芯片是与Intel8086配套使用的数值协处理器,体系结构复杂,有较大容量的嵌入式ROM存储器,考虑到与Intel8087的兼容性和管脚的限制,必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现,然后提出了芯片中嵌入式ROM电路的内建自测试,着重介绍了内建自测试的设计与实现,并分析了采用内建自测试的误判概率,研究结果表明,文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销,获得了满意的故障覆盖率,大大提高了整个芯片的可测性。 相似文献
7.
基于LabVIEW的存储器检测系统研究 总被引:2,自引:2,他引:0
针对某装备的存储器没有相应的测试设备,测试内容比较繁琐,设计了基于LabVIEW的存储器检测系统.硬件依托PXI测试总线予以实现,具有可靠性高,灵活性强的特点.针对组合存储器的特点,设计了专用的接口适配器,主要用于实现信号的同步和调理.文中分析了存储器的故障类型,研究March算法并进行了扩展.系统以LabVIEW作为软件工具,实现了对存储器的自动测试,用数据库实现了测试算法与测试程序的分离.该系统具有操作容易,可扩展性强等特点,有效提高了对某装备存储器的测试效率. 相似文献
8.
9.
10.
11.
The Transparent Online Memory Test (TOMT) introduced here has been specifically developed for online testing of word-oriented memories with parity or Hamming protection. Careful interleaving of a word-oriented and a bit-oriented test facilitates a fault coverage and a test duration comparable to the widely used March C- algorithm. Unlike similar methods TOMT actively exercises all bit cells in memory within one test period. Hence it not only detects soft errors but also functional faults and reliably prevents fault accumulation. Different variants of the basic TOMT algorithm are investigated in terms of fault coverage and test time. A prototype implementation for SRAM is introduced which-integrated into a standard processor/memory interface-autonomously performs the transparent online memory test. The trade-offs in terms of hardware overhead and memory access delay caused by this system integration are explored. 相似文献
12.
本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。 相似文献
13.
本文提出了一种新的缩短随机测试序列长度的方法,它是在找到电路中难测故障分布的基础上,通过对电路的初始输入施加概率不等的“1”信号,使这些难测故障的测试率升至最大值,这样,就可以达到提高故障覆盖率和缩短测试序列长度的目的。 相似文献
14.
Zarrineh K. Upadhyaya S.J. Chakravarty S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(6):845-857
Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework 相似文献
15.
New fault behaviors can emerge with the introduction of a drowsy mode to SRAMs. In this work, we show that, in addition to
the data-retention faults that can occur during the drowsy mode, open defects in SRAM cells can also result in new fault behaviors
when a memory is accessed immediately after wake-up. We first describe these new read-after-drowsy (RAD) fault behaviors and
derive their corresponding fault primitives (FPs). Then, we propose a new March test, called March RAD, by inserting drowsy
operations to a traditional test algorithm. Finally, the impact of the standby supply voltage on triggering the drowsy faults
in SRAM cells is investigated. It is shown that, as the supply voltage is reduced in the drowsy mode to further cut down leakage,
open defects with a parasitic resistance as small as 100 K Ω begin to cause faults. 相似文献
16.
阻变随机存储器(RRAM)中存在的故障严重影响产品的可靠性和良率.采用精确高效的测试方法能有效缩短工艺优化周期,降低测试成本.基于SMIC 28 nm工艺平台,完成了1T1R结构的1 Mbit RRAM模块的流片.详细分析了测试中的故障响应情况,并定义了一种故障识别表达式.在March算法的基础上,提出针对RRAM故障的有效测试算法,同时设计了可以定位故障的内建自测试(BIST)电路.仿真结果表明,该测试方案具有占用引脚较少、测试周期较短、故障定位准确、故障覆盖率高的优势. 相似文献
17.
A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper. 相似文献
18.
基于FPGA的SRAM测试电路的设计与实现 总被引:2,自引:0,他引:2
为了保证独立的SRAM模块或嵌入式SRAM模块功能的完整性与可靠性,必须对SRAM模块进行测试。介绍了一种基于Ahera DE2开发板的面向字节的SRAM测试电路的设计与实现。测试算法采用分为字内和字间测试两部分的高故障覆盖率March C-算法;设计的测试电路可由标准的JTAG(联合测试工作组)接口进行控制。设计的测试电路可测试独立的SRAM模块或作为BIST(内建自测试)电路测试嵌入式SRAM模块。验证结果表明该SRAM测试系统是非常高效的。 相似文献