5.8 GHz频率合成器的设计

介绍了5.8GHz频段及其应用领域.使用高件能的锁相频率合成芯片PLL801,微处理器STA2051,线性放大器STA-5063设计了一个5.8GHz频段的频率合成系统.分别介绍了PLL801和STA-5063的主要技术指标;阐述了该系统总体及各个部分的设计方案,并且针对射频信号的分布特性,对射频部分印制线做了阻抗匹配分析和设计.对实际设计出来的电路进行无线测试,结果显示该频率合成系统能够按照设计产生5.8GHz的信号.     

一种射频数字一体化宽带收发模块设计

针对中大型机载有源相控阵雷达系统的需求,提出一种射频数字一体化高集成宽带收发模块的设计方案。相比于传统雷达收发系统的射频、数字部分独立设计的方式,本设计将射频前端电路与数字收发电路集成在一个标准6U ASAAC插件内,以提高集成度、降低功耗。该模块可以实现2GHz以上瞬时带宽的宽带激励信号产生和宽带信号采集。本文先详细介绍了一体化收发模块的硬件组成和设计原理,其次介绍了FPGA软件设计思想,最后给出该模块的硬件测试和数据分析结果。     

多天线数字高清图传电路设计与实现

针对应急通信场景中图像、视频等宽带数据的稳定收发需求,基于软件无线电架构设计了2收2发天线的数字高清图传电路。该电路采用FPGA对基带数据进行64QAM调制,并通过AD9361射频收发器变频至5.8GHz进行收发。设计中使用ADS软件对AD9361的射频接收前端级联链路的阻抗匹配网络进行了仿真,在VIVADO软件中进行64QAM调制电路的设计与仿真。经测试,该电路能够进行图像数据的采集和收发,能够满足应急通信场景下高清图像的传输需求,具有体积小、通用性强的特点。     

面向DSRC的5.8GHz射频功率放大器仿真设计

基于winHBT工艺,利用ADS软件实现了用于DSRC系统5.8GHzRFPA的仿真设计,电路采用自适应线性化偏置电路,为核心电路提供了补偿电流和补偿电压。根据二端口网络S参数和Loadpull技术完成了功率放大器的匹配网络设计。最后在Cadence环境下完成了功放的版图设计。     

5.8GHz短距离无线收发系统的设计

详细介绍了一个以应答芯片CHR2244为核心的5．8GHz短距离无线收发系统的设计方案。该设计将实现上行FM,下行AM的无线数据收发功能。对天线模块、射频收发模块和数据链路控制分别进行了的阐述,同时对通信过程也进行了详细的描述。     

内置驱动的砷化镓大功率终端开关芯片设计与实现

介绍一种适用于多种制式无线终端产品的砷化镓单刀三掷射频开关芯片,主要用于收发支路的信道切换。芯片主要由单刀三掷开关和内置驱动电路组成,具有插损低、隔离度高、功率容量大以及功耗低等优点,可提供插损0.5dB@1.9GHz,0.85dB@5.8GHz,隔离度大于28dB@1.9GHz,20dB@5.8GHz,1dB压缩点大于38dBm,可应用于绝大多数移动通信终端设备中。     

基于ESIstream协议的高速串行收发接口

针对现有高速串行接口协议复杂、数据效率低的问题,基于ESIstream协议,提出一种应用于12~14位ADC/DAC新型收发接口的设计方案。采用14B/16B编解码算法,降低了数字电路的设计复杂度,将有效数据率提高到87.5%。加解扰器中,LFSR采用斐波纳契结构和多项式X17+X3+1来并行设计,降低了LFSR的工作时钟频率。采用Modelsim软件进行功能验证,并基于Design Compiler平台,采用TSMC 65 nm工艺库对电路进行综合。结果表明,该收发电路的单通道传输速度可达6.4 Gbit/s。     

一种新型双二极管5.8 GHz谐波抑制的整流电路

设计了一个5.8 GHz谐波抑制的新型整流电路。电路采用一对双二极管结合微带滤波设计,利用结构对称性实现偶次谐波抑制,结合扇形枝节三次谐波抑制,实现整流电路的四阶谐波抑制功能并具有宽带特性。实测和仿真结果基本一致,在5.8 GHz输入功率18 dBm时整流效率达到77.9%,并在5.725 GHz～5.875 GHz的ISM频段内的整流效率均超过74%。     

5.8 GHz CMOS混频器设计

介绍了CMOS混频器主要技术指标的设计思路和技术.采用O.18 μm CMOS工艺,使用Agilent公司的ADS软件设计出一种5.8 GHz CMOS混频器电路,结果表明,工作电压1.8 V时,RF频率5.8 GHz,本振频率5.78 GHz,中频频率20 MHz下,转换增益7.3 dB、输入1 dB压缩点-8.3 dBm,噪声系数8.7,工作电流小于5 mA,该电路已交付流片.     

一种级联型小数分频调制电路的设计实现

本文设计并实现了一个三阶的级联型调制电路用于实现5.8GHz小数分频锁相环。调制电路通过字长15bit的累加器作为基本单元,利用三级累加器的溢出值组成锁相环分频器的控制字序列。仿真结果表明,调制电路能够按照设计要求输出正确的分频序列,在分频比区间[0.1,0.95]内平均误差仅为0.4%。0.18μm CMOS工艺下,基于该调制电路实现的5.8GHz锁相环芯片能够准确锁定目标频点,相噪声性能为-109dBc/Hz。     

基于开关电容阵列的5.8GHz全集成LC压控振荡器设计

采用TSMC 0.18μm 1P6M RF CMOS工艺,完成了一种基于开关电容阵列的全集成LC压控振荡器的设计.版图后仿真结果表明,在1.8V电源电压下,电路核心功耗约为7.2mW,中心振荡频率为5.8GHz,在偏离中心频率1MHz处,该VCO的相位噪声为-121.8dBc/Hz,调谐范围为10.2%,满足交通专用短程通信系统的频段要求.     

An Improvement Energy Consumption Policy Using Communication Reduction in Wireless Body Sensor Network

Dedicated short-range communications (DSRC) is an important wireless technology for current and future automotive safety and mitigation of traffic jams. In this work, we have designed a Coplanar waveguide microstrip patch antenna with linear, upper and bottom and side slots for application in DSRC. The patch antenna was designed using glass epoxy substrate (FR4). Various parametric analyses such as the current distribution, reflection coefficient, radiation pattern on E- and H-plane as well as the realized gain (dB) were performed. The results were obtained by simulation using high-frequency structure simulator tool. The proposed antenna covers a frequency band of 5.8–5.9 GHz which is highly dedicated to the DSRC wireless communication technology for enhancement of safety of the automotive transport system. The designed antenna shows a good return loss of ??19 dB at 5.9 GHz.The designed antenna shows a promising gain, return loss and radiation pattern for use in DSRC for automotive transport systems.

     

A 5.8-GHz Quadrature Cross-Coupled Oscillator

This paper describes the implementation of a quadrature cross-coupled relaxation oscillator to be used in an OFDM RF front-end transceiver. A prototype of the oscillator was realized in a SiGe BiCMOS technology, and an oscillation frequency of 5.8 GHz was obtained which is 1/6 of the maximum f _T of the bipolar transistors. The circuit performance is evaluated by simulation and by experiment.     

A Dual-Band Coupled-Line Balun Filter

In this paper, a new type of device called dual-band coupled-line bandpass balun filter is presented. Based on the traditional coupled-line filter theory and Marchand balun configuration, a new device with both filter-type, as well as balun-type characteristics is proposed. The new device utilizes -type transmission-line stepped-impedance resonators to achieve a dual-band operation. Besides providing a simple design procedure for the device, its working mechanism is also revealed mathematically. A prototype balun filter operating at 2.4 and 5.8 GHz has been realized using traditional printed circuit board technology to validate the proposed concept and theory, showing promising application potentials for future multiband RF wireless transceiver modules. Experimental measurements show good agreement with analytical and computer simulations.     

基于LTCC技术的VCO研制

压控振荡器(VCO)在通信、雷达、测试仪器等领域中的应用非常广泛,但宽带调谐、小型化一直是VCO的设计瓶颈。文章描述了基于一种低温共烧陶瓷(LTCC)技术的微波振荡器的设计和制作,建立内埋式电感模型,并通过专用微波电路设计软件(AWR)对VCO电路进行分析,调整VCO匹配电路。测试结果表明,VCO输出频点为1.5～2.3GHz,输出相位噪声为-106dBc/Hz@100kHz,输出功率为13dBm。外形尺寸为6.9 mm×6.9 mm×1.2mm,远小于传统VCO体积,适应系统小型化的趋势。     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

一种新颖双馈电型PIN开关

微波光电二极管（PIN）开关速度和功率容量是相互矛盾的2个指标,为同时兼顾改善2个指标,结合半导体器件特性,采取PIN管芯两极同时馈电的设计形式（即双馈电型开关）,经过优化设计,研制出2 GHz～6 GHz单刀双掷PIN开关。与传统型开关电路相比,开关速度和功率容量都得到较好提升,为后续的工程应用奠定了基础。     

支持11ac的多功能家庭网关硬件方案设计

设计了一种家庭网关设备,可以实现PON（无源光网络）接入,同时提供有线上网和无线覆盖（WiFi 2.4 GHz 5.8 GHz）、电话、视频服务。用一个设备解决多个家庭设备的联网问题,而且速度较快。在周围用户较多的情况下,能够有较好地用户体验。由于此设备支持大功率WiFi11ac功能,输出功率达20 dBm,可以在2.4 GHz信号密集区域有效避开干扰,同时提供高达1.3 Gbit·s-1的连接速率,可以满足多用户大数据量传输的要求。     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。