Transimpedance amplifier with a compression stage for wide dynamic range optical applications

A high dynamic input transimpedance amplifier was implemented in 130 nm CMOS technology. The proposed TIA is an inverter with a diode connected NMOS and a gate controlled PMOS loads which is cascode connected with the inverter. The square law compression NMOS increases the input photocurrent up to 10 mA. The TIA has an integrated input referred noise current of 135 nA, 227 MHz bandwidth. The TIA shows a transimpedance gain of 59 dBΩ and a 97 dB dynamic range. The TIA consumes 2.3 mA from 1.5 V voltage supply.     

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2 V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33 ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100 MHz, the power consumption is 30 µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4 dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

A new CMOS differential current-mode AGC on the division operation based

A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results.     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers

In this paper, a low power Variable Gain Amplifier (VGA) circuit with an approximation to exponential gain characteristic is presented. It is achieved using current mirrors to generate appropriate current signals to bias the input stage of the VGA circuit working in triode region, and the output stage working in saturation region, respectively. The VGA circuit presented herein comes with a 549 μW maximum power consumption given a 1.8 V supply. Most important of all, it has a linear-in-dB 48-dB dynamic gain range per stage. The effect of the input trasconductance and the output resistance on the linearity of gain control is also discussed. This circuit is fabricated using a 0.18 μm standard CMOS process with a core area of 0.0045 mm².     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960 MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21 dBm output power and 35% power-added efficiency (PAE) with 3 V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.     

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro power-converters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

High rectifier output voltages with printed organic charge pump circuit

It is known that in many wireless organic electronic applications the required supply voltage is higher than the accessible signal amplitude. Therefore, voltage multiplier circuits are needed in many cases. We report a gravure printed organic charge pump circuit operating at 13.56 MHz suitable for rectified voltage amplification in printed electronic devices. The circuit, consisting of four diodes and four capacitors, has been monolithically printed using only high volume production compatible manufacturing methods. With 10 V AC input the output of the circuit at 13.56 MHz is 8.4 V and 11.8 V using 1 MΩ and 10 MΩ output loads, respectively. At 13.56 MHz the output voltage of the charge pump is three times higher than the output of a half-wave rectifier. The results demonstrate the possibility to print efficient high frequency (HF) charge pump circuits to meet the supply voltage requirements of the printed electronic applications.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules

This paper provides an insight into the operational robustness of commercially available SiC MOSFET power modules, during short-circuit (SC) and unclamped inductive switching (UIS) test environments. A set of five different power modules from three vendors rated from 1.2–1.7 kV and with various current ratings have been evaluated, where the possible failure mechanisms that cause the breakdown of the modules have been addressed. The SC pulse duration of the modules was gradually increased until the failure occurred. A critical short circuit energy in the order of 4.0–8.0 J was observed at a supply voltage of 800 V and a pulse duration of 4.0 μs. At lower supply voltage of 500 V, all modules survived until 10.0 μs. One of the modules, rated at 1.7 kV, survived SC tests at voltages up to 1000 V for a pulse duration of 4 μs, but failed when the supply voltage was increased to 1100 V. Prior to failure, a gate-source voltage drop has been recorded, which is associated with a high G-S leakage current. The main failure mechanism, however, is the thermal runaway which leads the devices into avalanche breakdown mode. During the UIS tests, multiple samples from the three vendors of the power modules failed. The failure of the modules was always caused by the external diode connected in parallel with the MOSFETs. One of the modules from the same vendor which does not have external diode and another module from a different vendor with external diode survived the UIS tests under nominal test conditions.