SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

I _DDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theI _DDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousI _DDQ testing, better defect diagnosis, and can be used for deep sub-micronI _DDQ testing.     

Modeling early failure in integrated circuit interconnect

A model based on the random electron–atom scattering is developed to characterize the effects of defects and grain sizes on electromigration caused failure in confined sub-micron metal interconnect lines. Our study shows that lines at sub-micron widths with a more uniform microstructure exhibit a greater consistency in time to failure. Taking mean time to failure and dispersion in time to failure as criteria, the simulator predicts that grain sizes in the 0.03–0.05 μm range are optimal for 0.125 μm wide Al alloy lines. We also argue that the early failure mechanism associated with the missing metal defects is eliminated by using a homogeneous, fine-grained material. The uniformity of the structure results in a mono-modal failure distribution and contributes to increasing the built-in reliability of the interconnect lines.     

Modeling gallium arsenide heterojunction bipolar transistor ledge variations for insight into device reliability

It is widely known that under normal bias conditions, GaAs heterojunction bipolar transistor (HBT) device degradation proceeds by a gradual buildup of defects in the base and base–emitter junction depletion regions. The buildup of these defects is associated with a solid-state phenomenon known as recombination enhanced defect reaction, which is the formation and migration of defects associated with nonradiative electron–hole recombination events. These defects are often associated with midgap traps, which serve as additional recombination centers for electron–hole pairs. The resulting increased recombination current is an additional base leakage current, which reduces current gain. By extension, a high electron–hole recombination density in a region with an initially high defect density––such as an unpassivated or poorly passivated base surface––will lead to quick device degradation.This paper reports the modeling of the effects of various different extrinsic base passivation ledge parameters––material composition, thickness, width, and spacing from ledge to base contact––to determine the microscopic effects these parameters have on electron–hole recombination density. Through this we can qualitatively predict the effects these parameters will have on HBT reliability.     

Facing the defect characterization and localization challenges of bridge defects on a submicronic technology (45 nm and below)

For very deep submicron technologies, 45 nm and less, bridge defects are getting more and more complex and critical. In order to find the exact root cause, accurate defect localization, precise understanding on the nature of the defect and its impact on the fine electrical behaviour of the device are mandatory. At these ultimate technologic nodes, failure analysis techniques show a real lack of efficiency on bridge defect localization while this precise location is one of the keys to find the defect root cause that allows correct implementation of corrective actions to improve yield and reliability.To face this challenge we have built a complete set of signatures related to advance Eldo simulations, performed measurement with ultimate failure analysis tools, fully characterized a microelectronic structure in advanced technology presenting a bridge defect and established a complete link between all these data and the failure location.     

Degradation of thin oxides during electrical stress

A bond-breaking phenomenon responsible for oxide degradation during electrical stress is considered as a multi-step process that includes generation of precursor breakdown defects by the injected electrons directly in the bulk oxide and the subsequent breakdown of the defect's bonds. Precursor defect generation is attributed to the capture/scattering of the injected electrons by the localized gap states associated with oxide structural imperfections. These precursor defects, represented by significantly elongated Si–O bonds or Si–Si bonds are shown to be unstable due to their vibrational excitation and polarization induced by temperature and an applied electric field, respectively; breakdown of the weak precursor defect's bonds results in the formation of the E^′ centers. The proposed model suggests that new precursor defects are preferentially created in the vicinity of the previously generated E^′ centers. This leads to the formation of defect clusters, which can grow and coalesce throughout the oxide, contributing to oxide leakage current and eventual oxide breakdown. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature and oxide thickness.     

Implant dose monitoring by MOS C–V measurement

The most critical parameter for deep sub-micron MOS field effect transistors is the threshold voltage, which is highly dependent on processing specifically, the ion implanted channel dose. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. MOS C–V methods are widely used for process ramp up and monitoring and MOS C–V doping profiling is an introduced method for monitoring of low dose implants. However, the failure of the depletion approximation in the near surface region implies that conventional MOS C–V measurements yield erroneous doping profiles in that region. Integrating MOS C–V doping profiles yields only a partial implant dose excluding the important near surface dose portion. Here, we report a new approach, which enables the determination of the entire implant dose, taking into account the crucial surface region. Moreover, the MOS threshold voltage can be obtained self-consistently. The method is also applicable to MOS structures with ultra thin gate oxides.     

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.     

Salicides: materials, scaling and manufacturability issues for future integrated circuits (invited)

In this paper we present an overview of the development of advanced salicide processes at Texas Instruments, addressing both Ti and Co salicides. Scaling issues, such as sheet resistance of deep sub-micron structures for Ti salicide and diode leakage on shallow junctions for Co salicide, are discussed, as well as processes developed to overcome these issues. The key material aspects controlling these variables are reviewed, such as Ti silicide phase formation and transformations and mechanisms of direct formation of C54 TiSi₂, which control sheet resistance, and silicide–silicon interface characteristics for Co salicide, impacting diode leakage. Implementation and manufacturability aspects are also discussed. We present advanced Ti and Co salicide processes with manufacturing and high yield capability demonstrated for sub-0.25 μm CMOS technologies. Process modifications that extend the applicability of these salicides to 0.1 μm CMOS are also presented.     

TFT-LCD阵列腐蚀性缺陷分析(英文)

在TFT-LCD的生产过程中,阵列金属被腐蚀是造成TFT-LCD产品缺陷(亮线、薄亮线等)的常见原因。文章对实际生产过程中阵列基板的一种典型腐蚀性缺陷,应用扫描电子显微镜(SEM)、聚焦离子束(FIB)和能谱仪(EDS)等工具,并且结合BO(Business Objects)、CIM(Computer Integrated Manufacturing)等数据统计软件进行了分析。确定了造成缺陷的原因是栅金属暴露在含氯元素的酸性气体中被腐蚀,还确定了酸性气体的泄露源,并且推断出其形成机理:腐蚀发生在栅金属刻蚀(Gate Etch)工艺和多层膜沉积(Multi-Deposition)工艺之间,随后的多层膜沉积工艺的抽真空过程促进了缺陷的进一步形成。另外,针对发生此种缺陷时的应急措施进行了探讨。     

Linewidth control effects on MOSFET ESD robustness

This paper advances state-of-the-art design layout considerations for deep sub-micron (0.25 μm) advanced single and stacked MOSFETs by addressing linewidth control effects on MOSFET ESD robustness. Advanced failure analysis tools are used to demonstrate linewidth bias. ESD robustness as a function of gate-to-gate spacings is addressed for the first time.     

Hierarchical test generation for combinational circuits with real defects coverage

This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits.     

Inversion phenomenon as a result of junction damages in neutron irradiated silicon detectors

This paper concerns with integrated microscopic investigations of bipolar junction damages in silicon detectors following neutron irradiation. This phenomenon was studied by means of an advanced contact potential difference method in atomic force microscopy (AFM). The obtained results were confirmed by topographical investigations also done by AFM and electron beam induced current, installed on a conventional scanning electron microscope. The most detailed structural investigations were carried out by means of scanning tunnel microscope. It was found that in the interval of neutron fluences, Φ,9.9×10¹⁰Φ3.12×10¹⁵ n/cm² the damage to the silicon lattice structure is accumulative, from small point defects to high defect accumulations. These defects consisted of large complexes of dislocation loops and vacancies, however, in the p–n junction region, only vacancies remained. This deterioration in the junction crystalline structure, resulted in a population inversion of the free charge carriers, from n- to p-type. The novelty of this research consists of the direct correlation, found between the structural defects and the mechanical and electrical properties of the diode junction.     

Electrical characterization of defects introduced during metallization processes in n-type germanium

We have studied the defects introduced in n-type Ge during electron beam deposition (EBD) and sputter deposition (SD) by deep-level transient spectroscopy (DLTS) and evaluated their influence on the rectification quality of Schottky contacts by current–voltage (I–V) measurements. I–V measurements demonstrated that the quality of sputter-deposited diodes are poorer than those of diodes formed by EBD. The highest quality Schottky diodes were formed by resistive evaporation that introduced no defects in Ge. In the case of EBD of metals the main defect introduced during metallization was the V–Sb complex, also introduced during by electron irradiation. The concentrations of the EBD-induced defects depend on the metal used: metals that required a higher electron beam intensity to evaporate, e.g. Ru, resulted in larger defect concentrations than metals requiring lower electron beam intensity, e.g. Au. All the EBD-induced defects can be removed by annealing at temperatures above 325 °C. Sputter deposition introduces several electrically active defects near the surface of Ge. All these defects have also been observed after high-energy electron irradiation. However, the V–Sb centre introduced by EBD was not observed after sputter deposition. Annealing at 250 °C in Ar removed all the defects introduced during sputter deposition.     

Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI–MOSFETs

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.     

Cross-sectional nanoprobing sample preparation on sub-micron device with fast laser grooving technique

Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.     

Electrically active defects generated by MERIE and RIE-mode plasmas in thin SiO2-Si structures

The effect of both RIE and high-density nonuniform magnetically enhanced reactive ion etching (MERIE)-type plasmas on the properties of thin oxide (11–13 nm) MOS capacitors as well as FETs without gate has been investigated. The results reveal the vulnerability of the oxide and its interface with Si to the plasma process — the interface is much more sensitive. The creation of defects in the form of fixed oxide charge, bulk traps, slow states and interface states is found. The damage level is a function of both the discharge conditions (including plasma exposure time) and the initial Si-SiO₂ structure parameters, the plasma conditions having a priority impact. The damage process is very rapid particularly in the first seconds (up to 30 s) of plasma exposure. The effects become highly process dependent as the plasma time increases. The plasma induced defects degrade the inversion carrier mobility and change the dominant scattering mechanism in the inversion channel. The damage leads to an excess leakage current and decreases the breakdown fields. A strong linear correlation between plasma induced leakage current and plasma created positive charge is detected. It is established that the build-up damage depends on plasma nonuniformity, but the non uniformity is neither the only nor the dominating factor. The nature of process induced defects and the influence of plasma components are discussed. It is proposed that generated interface states are mainly attributed to VUV and ion bombardment, whereas the high values of positive oxide charge are due to the charging effect. The type of plasma induced defects (oxide traps or interface states) and the energy distribution of interface states strongly depend on the relative contribution (or domination) of the different plasma components.A room temperature annealing of MERIE-type plasma induced interface states is established. The reduction depends only on the starting postplasma treatment level of interface states and the effects responsible for this reduction take place very close to the Si-SiO₂ interface. (The fixed oxide charge is stable and it does not change at all.) The process seems to be controlled by moisture transport to the Si-SiO₂ interface.By means of X-ray photo electron spectroscopy it is found that 5 min exposure of thin thermal SiO₂ to N₂-RIE mode plasma causes structural modifications, which manifest only as a deterioration of oxide quality without actual nitration of the oxide. The presence of a small constant amount of SiO species through the oxide and a broadening of Si-SiO₂ interface region are detected.The nature of the electrically active plasma induced defects by both plasma processes — RIE and MERIE is equal — the bond defects in the oxide and at the interface: the oxide charge is associated with E′ centers and the interface states with P_b centers.     

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Increasing in device parameter variations is the critical issue in very deep sub-micron regime due to continue scaling of the transistor dimensions. The overall performance yield of the logic circuit is diminished by raising leakage current and variability issues in scaled devices. In this article; we have proposed an approach called INDEP, based on Boolean logic calculation for the input signals of the extra inserted transistors between the pull-up and pull-down network of the CMOS logic. INDEP approach is not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. Various process, voltage and temperature (PVT) variations are analyzed at 22 nm BSIM4 bulk CMOS PTM technology node for chain of 5-inverters using HSPICE tool. Several guidelines are provided to design the variability aware CMOS circuits in nanoscale regime by considering the leakage current variation. INDEP approach works effectively in both active as well as standby state of the circuit and keeping the modal performance characteristics of the CMOS gate. The electrical simulation results show that our proposed INDEP approach is less susceptible to PVT variations as compared to conventional circuit. The Monte-Carlo simulation results confirm that average INDEP leakage current reduction is 62.31% at ±20% PVT variations under 3σ Gaussian distribution for chain of 5-inverters.     

Static fault localization of subtle metallization defects using near infrared photon emission microscopy

In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable I_DD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.     

Bond strain and defects at interfaces in high-k gate stacks

The performance and reliability of aggressively-scaled field effect transistors are determined in large part by electronically-active defects and defect precursors at the Si–SiO₂, and internal SiO₂–high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond strain-driven bonding interfacial self-organizations that take place during high temperature annealing in inert ambients. The interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO₂, and (i) crystalline Si, and (ii) non-crystalline and crystalline alternative gate dielectric materials.     

Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET) measured by gated-diode configuration

In this paper the hot carrier degradation behavior of the SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET’s) is investigated based on the forward gated-diode configuration. With peak diode current as an indicator, the hot carrier induced degradation of SOI n-DTMOSFET’s is compared with the corresponding SOI nMOSFET’s. Due to the connection of the gate and the body and thus the positive-biased source–body and drain–body junction, the SOI n-DTMOSFET’s exhibit lower peak diode current than the conventional counterparts, showing smaller generated defect density and thus lower hot carrier induced degradation. The generated defect distribution in SOI n-DTMOSFET is analyzed. It is shown that despite of the tied gate-body, the peak of the generated defect density tends to lie in the gate-to-drain overlap region. The defect distribution exerts different influences on the diode current of the long channel device and short channel device with different electric field. Moreover, even with the positive biased body, the generated defects in SOI DTMOSFT are more apt to flow to front interface rather than back interface, resulting in the more severe degradation of the front interface in SOI n-DTMOSFET’s. This gives the main flow direction of the generated defects.