Design and Implementation of a Novel Area-Efficient Interpolator

提出了一种插值滤波器的设计与实现的新方法,并最终将其实现.该方法适合于过采样数模转换器.为减小芯片面积及设计复杂度,采用一种等同子滤波器级联设计方法,并对其改进.同时,提出了一种新型的等同子滤波器实现结构,进一步减少了芯片实现所需的硬件.测试结果表明,芯片达到了设计指标,节省了芯片面积,并显示出良好的噪声抑制性能.该数字插值滤波器已经被成功应用于一款过采样数模转换器.     

一种应用于音频的DAC中插值滤波器的设计

设计了一种应用于24位音频DAC中实现128倍过采样的插值滤波器,该插值滤波器采用多级插值的方法,根据前后级采样速率不同的特点,选择不同的滤波器结构.采用一种基于CSD编码的方法来实现一种多相结构,这种多相结构不需要乘法器.该方法在减小了控制系统复杂性的同时也减小了芯片的面积.仿真结果表明,该插值滤波器的通带纹波和阻带衰减都达到了设计要求.     

用于高精度∑-△数模转换的多级插值滤波器的设计技术

提出了一种用于20bit ∑-△数模转换器中的内插滤波器的有效实现方法,内插滤波器的过采样率为128.该方法使用多级结构以降低滤波器系数的复杂度和有限字长效应.同时提出了基于系数混合基分解的多相半带滤波器的无乘法器实现方法,它降低了控制逻辑的复杂程度,并大大节省了芯片面积.芯片采用0.13μm CMOS工艺实现,整个插值滤波器面积小于0.63mm2.整个电路系统仅用简单的硬件单元实现,且结构规整,这有利于大规模集成电路制造,并可应用于高精度数据转换电路中.     

用于高精度Σ-Δ数模转换的多级插值滤波器的设计技术

提出了一种用于20bit Σ-Δ数模转换器中的内插滤波器的有效实现方法，内插滤波器的过采样率为128. 该方法使用多级结构以降低滤波器系数的复杂度和有限字长效应. 同时提出了基于系数混合基分解的多相半带滤波器的无乘法器实现方法，它降低了控制逻辑的复杂程度,并大大节省了芯片面积. 芯片采用0.13μm CMOS工艺实现，整个插值滤波器面积小于0.63mm2. 整个电路系统仅用简单的硬件单元实现，且结构规整，这有利于大规模集成电路制造,并可应用于高精度数据转换电路中.     

用于高精度Σ-Δ数模转换的多级插值滤波器的设计技术(英文)

提出了一种用于20bitΣ-Δ数模转换器中的内插滤波器的有效实现方法,内插滤波器的过采样率为128.该方法使用多级结构以降低滤波器系数的复杂度和有限字长效应.同时提出了基于系数混合基分解的多相半带滤波器的无乘法器实现方法,它降低了控制逻辑的复杂程度,并大大节省了芯片面积.芯片采用0.13μm CMOS工艺实现,整个插值滤波器面积小于0.63mm2.整个电路系统仅用简单的硬件单元实现,且结构规整,这有利于大规模集成电路制造,并可应用于高精度数据转换电路中.     

用于高精度∑-△数模转换的多级插值滤波器的设计技术

提出了一种用于20bit ∑-△数模转换器中的内插滤波器的有效实现方法,内插滤波器的过采样率为128.该方法使用多级结构以降低滤波器系数的复杂度和有限字长效应.同时提出了基于系数混合基分解的多相半带滤波器的无乘法器实现方法,它降低了控制逻辑的复杂程度,并大大节省了芯片面积.芯片采用0.13μm CMOS工艺实现,整个插值滤波器面积小于0.63mm2.整个电路系统仅用简单的硬件单元实现,且结构规整,这有利于大规模集成电路制造,并可应用于高精度数据转换电路中.     

∑△DAC中插值滤波器的设计

本文设计了一种用于分辨率为20bit,采样率为48kHz,信噪比为102dB的∑△DAC(数模转换器)中的数字插值滤波器.利用多项插值器原理,采用128(插值,并利用SRAM和PLA设计了8倍插值,大大减少了所需硬件及芯片面积.仿真结果表明能够满足性能要求.     

新型双声道音频Σ-ΔDAC小面积插值滤波器的设计实现

该文提出了一种新型双声道音频Σ-Δ数模转换器(DAC)小面积插值滤波器设计方法。该方法采用左右两个声道复用一个插值滤波器的新型结构,并利用存储器实现第1级半带滤波器,从而降低芯片的实现面积。提出重新排序方法,保证复用后两个声道的同步。设计在TSMC 0.18μm 1.8 V/3.3 V 1P5M CMOS工艺上实现,测试信噪比为106 dB,数字部分芯片的面积仅为0.198 mm2,功耗为0.65 mW。这种设计方法降低了Σ-ΔDAC系统中数字部分的面积和功耗,给模拟部分留有较大的设计裕量,这对模数混合系统的设计具有重要的意义。     

一种100dB输出动态范围的1.5bit功率数模转换器

介绍了一种1.5bit的双声道过采样数模转换器.它把过采样数模转换器和D类功率放大器这两部分集成在一起,不需要额外的低通滤波器即可直接驱动耳机扬声器等语音设备.它无需消耗直流功耗,对于常用的8Ω扬声器负载,其最大输出功率可达436mW,输出动态范围大于100dB.该电路采用TSMC 0.18μm工艺实现.芯片面积为0.28mm2,其中数字电路的电源电压为1.8V,D类功率放大器的电源电压为3.3V.     

一种100dB输出动态范围的1.5bit功率数模转换器

介绍了一种1.5bit的双声道过采样数模转换器.它把过采样数模转换器和D类功率放大器这两部分集成在一起,不需要额外的低通滤波器即可直接驱动耳机扬声器等语音设备.它无需消耗直流功耗,对于常用的8Ω扬声器负载,其最大输出功率可达436mW,输出动态范围大于100dB.该电路采用TSMC 0.18μm工艺实现.芯片面积为0.28mm2,其中数字电路的电源电压为1.8V,D类功率放大器的电源电压为3.3V.     

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.     

A 16-bit 250-kHz delta-sigma modulator and decimation filter

This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-μm CMOS technology. It achieves a dynamic range of 94 db     

Optimum FIR and IIR multistage multirate filter design

A theorem is introduced which is useful in deriving equivalent multirate filter structures. Frequency responses of multistage multirate filters are derived and defined by deriving their equivalent one-stage filters. A design principle is proposed to reduce filtering requirements at each stage and move the filter operations to low-sampling-rate stages and thus result in a lower arithmetic rate. Optimum FIR and IIR multistage multirate filter designs are developed based on this principle. The new design has a one-point passband specification for each decimator and/or interpolator stage resulting in a wider transition region and lower filter order. Examples are given to explain the design procedure, and comparisons are made to show the superiority of the new filters.     

A Design Approach for Power-Optimized Fully Reconfigurable $Delta Sigma$ A/D Converter for 4G Radios

This paper presents a novel design approach for fully reconfigurable low-voltage delta-sigma analog-digital converters for next-generation wireless applications. This approach guides us to find the power-optimal solution corresponding to the specifications of various wireless standards by exploring single-loop feedback and feedforward topologies with different filter order, number of quantizer bits, and oversampling ratios. Unlike previous multimode designs, this approach provides a better power efficiency. Based on this approach, a system-level design of a digitally programmable delta-sigma modulator for 4G radios is presented.     

微控制器PWM接口实现高分辨率D/A 转换器方法研究

本文针对嵌入式应用中PWM (Pulse-Width Modulation)方式DAC(Digital-to-Analog Converter)和独立DAC芯片选择问题,提出了通过插值方式和多PWM组合方式提高PWM方式DAC分辨率的方法;分析了PWM信号频谱,提出了模拟滤波器设计原则与方法.以MCU(Micro Control Unit)的PWM通道方式实现DAC,经过数据分析证明此方法稳定可靠.     

Cascade delta-sigma modulator with pseudo-differential comparator-based switched-capacitor gain stage

A low-power, multi-stage delta-sigma modulator with comparator-based switched-capacitor (CBSC) gain stages is presented. The presented design eliminates the need for operational amplifiers and replaces them by comparators with current sources at their outputs to alleviate the effects of continued technology scaling on analog and mixed-signal circuits. The proposed technique significantly reduces power consumption and can be applied to switched-capacitor delta-sigma modulators of arbitrary order. Based on the proposed methodology, a 2-1 cascade, single-bit, pseudo-differential switched-capacitor delta-sigma modulator is developed and achieves a SNDR of 76.8 dB with an oversampling ratio of 64 at a clock frequency of 8 MHz.     

Using fractional delay to control the magnitudes and phases of integrators and differentiators

The use of fractional delay to control the magnitudes and phases of integrators and differentiators has been addressed. Integrators and differentiators are the basic building blocks of many systems. Often applications in controls, wave-shaping, oscillators and communications require a constant 90deg phase for differentiators and -90deg phase for integrators. When the design neglects the phase, a phase equaliser is often needed to compensate for the phase error or a phase lock loop should be added. Applications to the first-order, Al-Alaoui integrator and differentiator are presented. A fractional delay is added to the integrator leading to an almost constant phase response of -90deg. Doubling the sampling rate improves the magnitude response. Combining the two actions improves both the magnitude and phase responses. The same approach is applied to the differentiator, with a fractional sample advance leading to an almost constant phase response of 90deg. The advance is, in fact, realised as the ratio of two delays. Filters approximating the fractional delay, the finite impulse response (FIR) Lagrange interpolator filters and the Thiran allpass infinite impulse response (IIR) filters are employed. Additionally, a new hybrid filter, a combination of the FIR Lagrange interpolator filter and the Thiran allpass IIR filter, is proposed. Methods to reduce the approximation error are discussed.     

A high-resolution interpolator for incremental encoders based onthe quadrature PLL method

This paper presents a new high-resolution interpolator for incremental encoders based on the quadrature phase-locked loop method proposed by Emura. Until now, this method has been applied to controllers of high-precision servomechanisms and has shown excellent performance. In this paper, the authors apply the method for the first time to an interpolator for incremental encoders. The experimental results show that high-speed interpolation is possible, with a maximum output frequency of 25 MHz-20 times higher than that of conventional interpolators. The interpolator proposed was also tested for noise rejection with a high-speed numerically controlled gear grinding machine, and has shown good noise rejection capability. This paper presents the design of the interpolator and the experimental results