基于AAC比特流的音频信号Hiss噪声抑制方法

基于AAC比特流,提出了一种压缩域音频Hiss噪声抑制方法。该方法的输入为含噪音频的AAC比特流,输出为增强音频的AAC比特流。首先,利用修正的绝对中值标准差（MMAD, modified median absolute deviation）估计Hiss噪声,其次,利用修正的离散傅里叶变换（MDFT, modified discrete Fourier transform）计算听觉掩蔽阈值参数,最后,根据参数软阈值方法得到增强的AAC比特流,并用于AAC解码器得到最终的增强音频信号。主观和客观测试结果表明,所提出的方法能有效去除AAC解码音频信号中的Hiss噪声,其性能明显优于现有的几种Hiss噪声消除方法。     

基于MPEG-AAC编码器的压缩域音频增强方法

本文基于MPEG-AAC音频编解码器,提出了一种压缩域的音频增强方法.首先,对含噪音频信号的比特流进行解码,得到含噪音频信号的MDCT系数;然后,利用修正的加权递归平均（Modified Weighted Recursive Averaging,MWRA）方法估计噪声功率;再者,利用基于听觉掩蔽原理的自适应β-阶双曲余弦（COSH）统计模型,对含噪音频的MDCT系数进行增强处理;最后,将增强后的MDCT系数重新量化编码,得到用于解码的增强比特流实验结果表明,本文提出的方法能有效去除AAC解码音频信号中的多种背景噪声,其性能明显优于参考方法.     

H.264基本档次码流解析的专用处理器设计

针对解析H.264基本档次码流提出一种专用处理器的设计方案,它采用软/硬件联合设计的方法.使硬件电路解码模块可实现每个时钟周期从码流中解析出1个码字的处理速度,比采用树形结构的纯软件方案提高了50倍.     

Bit-stream allocation methods for scalable video coding supporting wireless communications

The demand for video access services through wireless networks, as important parts of larger heterogeneous networks, is constantly increasing. To cope with this demand, flexible compression technology to enable optimum coding performance, especially at low bit-rates, is required. In this context, scalable video coding emerges as the most promising technology. A critical problem in wavelet-based scalable video coding is bit-stream allocation at any bit-rate and in particular when low bit-rates are targeted. In this paper two methods for bit-stream allocation based on the concept of fractional bit-planes are reported. The first method assumes that minimum rate-distortion (R–D) slope of the same fractional bit-plane within the same bit-plane across different subbands is higher than or equal to the maximum R–D slope of the next fractional bit-plane. This method is characterised by a very low complexity since no distortion evaluation is required. Contrasting this approach, in the second method the distortion caused by quantisation of the wavelet coefficients is considered. Here, a simple yet effective statistical distortion model that is used for estimation of R–D slopes for each fractional bit-plane is derived. Three different strategies are derived from this method. In the first one it is assumed that the used wavelet is nearly orthogonal, i.e. the distortion in the transform domain is treated as being equivalent to the distortion in the signal domain. To reduce the error caused by direct distortion evaluation in the wavelet domain, the weighting factors are applied to the used statistical distortion model in the second strategy. In the last strategy, the derived statistical model is used during the bit-plane encoding to determine optimal position of the fractional bit-plane corresponding to refinement information in the compressed bit-stream. Results of selected experiments measuring peak signal to noise ratio (PSNR) of decoded video at various bit-rates are reported. Additionally, the PSNR of decoded video at various bit-rates is measured for two specific cases: when the methods for bit-stream allocation are used to assign quality layers in the compressed bit-stream, and when quality layers are not assigned.     

Efficient FPGA implementation of bit-stream multipliers

A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables     

嵌入式比特流混沌加密算法的研究与仿真

提出混沌与嵌入式比特流相结合的加密算法.首先,将原始图像进行二维小波变换后,转换成小波域上的小波系数,然后对小波系数进行嵌入零树小波编码.接着,使用分段线性混沌映射产生二进制混沌序列,对码流分组加密,该算法具有较高的安全性.仿真试验结果表明,该算法能够得到令人满意的结果.     

Investigation into the Use of Hybrid Solutions for ΣΔ A/D Converter Testing

ΣΔ ADCs are now extensively used in electronic system applications requiring high resolution analogue to digital interfaces. Many of these applications require low cost solutions that imply the need for efficient production test strategies for verifying performance specifications. Industrial state-of-the-art is based on DSP testing to extract dynamic performance such as THD and SNR from an FFT on a sampled bit-stream from the decimator output. This method is computationally expensive and as resolution increases, the total number of samples required also increases thus pushing total test time beyond acceptable limits. This paper proposes an alternative hybrid solution based on an initial low-cost wafer level screening test followed by a DSP based technique on marginal devices based on alternative DSP transforms. The screening test is applied to the high-frequency bit-stream output of the ΣΔ modulator and has potential for on-chip implementation. Relatively simple algorithms and cross-correlation techniques are used that can associate specific changes in the bit-stream pattern to key failure modes affecting dynamic performance parameters. A simplified supplementary DSP test for marginal devices is proposed that is less computationally intensive than FFT analysis.     

一种基于混合整型变换和3D-SPIHT的高光谱图像嵌入式无损压缩方法

利用高光谱图像空间、谱间相关性不同的特点,本文提出了一种基于混合整型变换和三维分层树集合划分算法(3D-SPIHT)的高光谱图像无损压缩方法,首先将波段进行分组,针对每一分组,采用不同的整型变换技术去相关,然后对变换系数进行系数重组,采用高效的基于小波系数特点的3D-SPIHT编码方法得到嵌入式码流,具有一定的抗误码性能.实验结果表明,该方法能够有效的去除高光谱图像的空间和谱间相关性,与现有的国际标准JPEG-LS、JPEG2000和基于三维离散余弦变换(3D-DCT)或三维离散小波变换(3D-DWT)的编码方法相比,压缩后的平均比特率均有明显降低.     

Absolute value coding for robust and scalable video coding

Absolute value coding is introduced as a method for significantly reducing temporal drift within a motion compensated predictive video codec in the presence of loss. Drift reduction both improves error resilience and enables scalability by omission of parts of the bit-stream. In conjunction with matching pursuits, the system can be used to provide a displaced frame difference codec using fixed length codewords, which further improves error resilience and facilitates simple bit-stream editing.     

高清晰度电视信源压缩编解码系统的研究

本文提出了一种码率不高于２２Ｍｂ／ｓ的基于ＭＰＥＧ－２标准的数字高清晰度电视视频编解码实验系统，重点研究了帧／场自适应ＤＣＴ变换及相应的帧／场扫描方式、量化器设计、码率控制及缓存器控制策略、数据流层结构等关键技术。     

Use of comb filters for efficient VLSI implementation of reducedclock frequency noise shapers

The use of comb filters as an elegant means of reduced clock frequency noise-shaping without excessive hardware overhead is presented. The significance of the method is illustrated using second order noise-shaping characteristics. A 256 times oversampled and noise-shaped bit-stream sequence is obtained by running a second order noise shaper at a clock frequency four times lower than that of the bit-stream sampling rate, in association with an in-loop multi-bit to four single bit transformation at a tolerable hardware overhead     

一种符合ITU-T指标要求的嵌入式立体声语音频编码方法

 基于国际电信联盟标准化组织(ITU-T)编码标准G.729.1,本文提出了一种嵌入式变速率立体声语音与音频编码方法.本算法利用G.729.1和改进的调制叠接变换(Modulated Lapped Transform,MLT)编码技术对输入信号的中值与边带信息进行分层编码,形成具有嵌入式结构的码流.编码器可处理宽带和超宽带的立体声信号,宽带立体声信号编码的最大码率为48kb/s,超宽带立体声信号编码的最大速率为64kb/s.实现结果表明,本编码器的编码质量均达到了ITU-T对G.EV-VBR立体声编码的指标要求.     

Optimal base-station locations in two-tiered wireless sensor networks

We consider generic two-tiered wireless sensor networks (WSNs) consisting of sensor clusters deployed around strategic locations, and base-stations (BSs) whose locations are relatively flexible. Within a sensor cluster, there are many small sensor nodes (SNs) that capture, encode, and transmit relevant information from a designated area, and there is at least one application node (AN) that receives raw data from these SNs, creates a comprehensive local-view, and forwards the composite bit-stream toward a BS. This paper focuses on the topology control process for ANs and BSs, which constitute the upper tier of two-tiered WSNs. Since heterogeneous ANs are battery-powered and energy-constrained, their node lifetime directly affects the network lifetime of WSNs. By proposing algorithmic approaches to locate BSs optimally, we can maximize the topological network lifetime of WSNs deterministically, even when the initial energy provisioning for ANs is no longer always proportional to their average bit-stream rate. The obtained optimal BS locations are under different lifetime definitions according to the mission criticality of WSNs. By studying intrinsic properties of WSNs, we establish the upper and lower bounds of maximal topological lifetime, which enable a quick assessment of energy provisioning feasibility and topology control necessity. Numerical results are given to demonstrate the efficacy and optimality of the proposed topology control approaches designed for maximizing network lifetime of WSNs.     

最新的ITU-T嵌入式变速率语音编码关键技术

介绍了ITU-T的新一代语音编码标准G.729.1的编码器、译码器原理,讨论了此标准实现码流嵌入式所采用的关键技术:嵌入式的码激励线性预测编码技术、时域频带扩展技术以及时域混叠抵消的预测变换编码技术,并通过客观评测验证了G.729.1语音编码标准的高性能。     

Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six- input look-up tables.     

Optimum cyclic redundancy codes for noisy channels (Corresp.)

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16-bit ADCCPt polynomial is designed for digital links that already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of the resulting digital circuit may be much lower. This leads to the consideration of 3-byte (24-bit) and 4-byte (32-bit) polynomials. Generator polynomials of a certain class are found that have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular polynomials for 24-bit and 32-bit redundancies are exhibited, of weight and distance 6 in the 24-bit case and weight 10 and distance 8 in the 32-bit case.     

一种新型DSP指令结构及数据通道

针对可以处理不同位宽数据的DSP结构,提出了一种提高指令编码密度的方法,使设计的DSP指令减少了32条。另外提出了两种能同时实现16bit乘法累加运算和32bit乘法累加运算的数据通道结构。对这两种数据通道都用Verilog语言进行了模拟仿真。     

一种具有旋转不变性的压缩域纹理图像分类方法

该文提出了一种具有旋转不变性的、基于DCT压缩域的纹理图像分类方法。此方法主要是在DCT压缩域中合理组织频率系数,使其具有与小波分解相类似的图像多分辨率结构,由此设计了抗旋转能力强的纹理图像分类算法。这些操作直接在游程长编码(RLE)形成的码流上进行,处理的数据量较少,处理速度快。实验结果表明,这种分类方法具有较高的准确性。     

周期性业务流通过ATM复用器的时延抖动分析

ＡＴＭ通信网中需要传送多种业务，其中有一类是具有连续比特流的业务，这种业务的发送信元到达时间是周期性的，本文分析了一种周期性信元流通过ＡＴＭ复用器的排队模型，得出信元流排队时延的概率分布，时延抖动的自相关函数的功率谱。     

Progress in high-speed and high-resolution CMOS data converters

This paper presents an overview of the status of high-speed and high-resolution CMOS data converters. Techniques and achieved performance are compared using power consumption per step of resolution as a key parameter. The effort in optimizing this quality factor is evident, because of urgency of portable system requirements. Trends towards low-power design and bit-stream processing are also considered.