共查询到18条相似文献,搜索用时 765 毫秒
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提出了一种高电源纹波抑制比的低压差线性稳压器.该低压差线性稳压器通过提高带隙基准的电源抑制比以达到提高LDO(低压差线性稳压器)低频电源纹波抑制的能力.在TSMC 0.18μm CMOS工艺下进行了仿真验证,仿真结果表明,该LDO最大负载电流可以达到80mA,当负载电流在0~80mA范围内变化时,开环相位裕度均大于64°,证明了低压差线性稳压器的高稳定性.当负载电流从0mA跳变到80mA时,系统的输出电压过冲仅为15mV,环路响应时间仅为0.5μs.当负载电流为80mA,测得10kHz时的电源纹波抑制比为-60.82dB,100kHz时LDO的电源纹波抑制比为-57.66dB. 相似文献
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《固体电子学研究与进展》2016,(3)
设计了一种应用于射频功放的负压低压差线性稳压器。通过设计负压带隙基准源,以及采用预稳压模块,有效地降低了电源电压对负压LDO输出电压的影响;通过优化控制环路中的功率管尺寸、误差放大器以及电阻反馈网络等措施,在保证大电流输出的前提下,有效地降低了负压LDO的压差,提高了稳压器的整体性能。采用CSMC 0.5μm CMOS工艺进行设计并实现,测试结果表明,当输出电流为500mA,输出电压为-3V时,压差仅为170mV。 相似文献
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设计了一种应用于射频功放的负压低压差线性稳压器。通过设计负压带隙基准源,以及采用预稳压模块,有效地降低了电源电压对负压LDO输出电压的影响;通过优化控制环路中的功率管尺寸、误差放大器以及电阻反馈网络等措施,在保证大电流输出的前提下,有效地降低了负压LDO的压差,提高了稳压器的整体性能。采用CSMC 0.5μm CMOS工艺进行设计并实现,测试结果表明,当输出电流为500mA,输出电压为-3V时,压差仅为170mV。 相似文献
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为了延长便携式、可穿戴医疗设备的待机时间,设计了一种具有超低静态电流的低压差(LDO)线性稳压器。采用误差放大器与基准电路相结合的结构,在降低静态电流的同时减小芯片面积;其次,利用负载检测模块,降低了空载及轻载时过温保护和过流保护等模块的静态电流。采用自适应偏置电流技术来动态调整稳压环路各支路的工作电流以及零点频率补偿方式,解决了静态功耗与瞬态响应和环路带宽间的矛盾。该LDO线性稳压器采用0.35μm CMOS工艺进行流片加工,测试结果表明,该LDO线性稳压器静态电流为700 nA,最大负载电流为150 mA,轻载与满载跳变时上过冲电压为63 mV,下过冲电压为55 mV。 相似文献
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设计了一款适用于高压电源芯片的无片外电容快速瞬态响应型自启动低压差线性稳压器(LDO)。该LDO与芯片内部基准电路形成自供电自偏置环路,节省了芯片面积,适用电压范围为3.6~16.0 V,输出电压为5.10 V,具有功耗低、带宽宽等特点。电路采用Hspice进行仿真验证,在典型工艺角下,负载电流经100 mA/μs突变时,输出电压突变量最大为98 mV;在两种极端工艺角下,输出电压突变量最大为111 mV。环路特性仿真验证表明,该LDO带宽为3.6 MHz,3 dB带宽为2.5 MHz,相位裕度约75°,片内补偿电容仅3 pF。 相似文献
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分析、总结了以低压差线性稳压器和开关电源为基础模块的便携式设备用电源管理芯片的发展现状.围绕高效率、高功率密度、快速瞬态特性以及高电源抑制等需求,从环路控制、电源抑制比增强、动态提升模块以及全集成等角度分析了便携式设备电源管理系统的拓扑架构及优化设计方法.在新架构方面,首先,分别讨论了混合架构低压差线性稳压器和混合架构... 相似文献
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A novel power supply transform technique for high voltage IC based on the TSMC 0.6μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/℃. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well. 相似文献
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Alon E. Kim J. Pamarti S. Chang K. Horowitz M. 《Solid-State Circuits, IEEE Journal of》2006,41(2):413-424
Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable tradeoffs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulator's amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifier's gain to reject supply noise is effectively restored. Analysis shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised, and experimental results from a 90 nm SOI test chip confirm that with the same power consumption, the proposed regulator achieves at least 4 dB higher supply rejection than the previous regulator design. Furthermore, simulations show that if not for other supply rejection-limiting components in the PLL, the supply rejection improvement of the proposed regulator is greater than 15 dB. 相似文献
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无人机合成孔径雷达接收机对电源的纹波和频谱特性要求比较高,一般采用线性电源。该文提出运用开关电源方案解决无人机合成孔径雷达接收机的电源问题,采用推挽和CUK变换器向接收机内的设备供电,可以减小体积、降低重量、提高效率,利用CUK变换器和低噪声低压降稳压器射频噪声低的特点,解决了低噪声放大器和压控振荡器对电源纹波和频谱特性要求高的难题。 相似文献
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设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。 相似文献
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G. H. Zare Fatin Z. D. Koozehkanani H. Sjöland 《Analog Integrated Circuits and Signal Processing》2010,65(2):239-244
This paper presents a novel compensation design for regulators, i.e., modified NMCF (nested Miller compensation with feedforward
Gm stage), resulting in a linear LDO (low dropout) regulator whose performance is independent of the off-chip capacitor and
its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the
sufficient phase margin of the LDO regulator. Besides, the transient response become faster. The analysis of the stability
is derived to solidify the proposed design. The proposed design is implemented using TSMC 0.35 μm 2P4M CMOS process. The results
verify the performance and the stability on silicon. The power supply rejection ratio is 25 dB @ [200 Hz, 3 MHz], [50 Ω, 500
Ω] provided that the input voltage varies from 4 to 5 V. 相似文献