一种高精度Σ-ΔA/D转换器的数字滤波器设计

本文设计并实现了一种适用于高精度Σ-ΔADC的低资源数字滤波器。该滤波器采用多级多采样率结构,由级联梳妆滤波器(CIC)、FIR补偿滤波器以及半带滤波器级联组成。此外,为节约资源,采用乘法器时分复用和CSD编码技术,以降低面积和功耗。基于SIMC 0.18um工艺,对电路进行仿真。仿真结果表明,工作频率6.144MHz,带宽20KHz时,可以实现128倍信号抽取,输出信号信噪比可达16位以上。与同类型抽取滤波器相比,本设计具有高精度、低功耗的优点。     

高速∑-ΔDAC中插值滤波器的设计

基于ISO/IEC18000-6C协议设计了一种最高工作频率为48 MHz可用于UHF RFID系统的∑-ΔDAC的插值滤波器。该滤波器采用级联补偿滤波器、半带滤波器和级联积分梳状(CIC)滤波器的系统结构以降低设计复杂度。基于正则符号编码(CSD)技术将前两级滤波器中的乘法运算转化为移位相加以降低功耗和面积。同时,对CIC滤波器进行结构优化,进一步降低功耗。整个设计在MATLAB下完成系统仿真,并经过代码仿真、逻辑综合、布局布线等一系列数字流程。整个滤波器用标准0.18μm CMOS工艺实现,核心芯片面积小于0.52 mm2功耗约为5 mW。经仿真验证,满足性能要求。     

基于FPGA的FIR数字滤波器的优化设计

提出采用正则有符号数字量（CSD）编码技术实现FIR滤波器。首先分析了FIR数字滤波器理论及常用设计方法的不足,然后介绍了二进制数的CSD编码技术及其特点,给出了其于CSD编码的定点常系数FIR滤波器设计过程,使用VHDI,语言实现了该常系数滤波器的行为描述。最后在Max＋PlusⅡ环境下进行实验仿真和验证,与DA和2C编码算法比较结果表明,用CSD编码技术实现的滤波器可以有效提高运算速度并降低FPGA芯片的面积占用。     

0.18μm CMOS Σ-Δ ADC用数字抽取滤波器设计

采用标准0.18μm CMOS工艺,设计了一种应用于UHF RFIDΣ-Δ模数转换器的数字抽取滤波器,并完成其前后仿真、逻辑综合、布局布线及版图实现等全流程.该滤波器主要实现滤波和降采样功能,由梳状滤波器、补偿滤波器和半带滤波器级联组成.合理选择各级滤波器的结构、阶数并采用规范符号编码(CSD)对其系数进行优化.仿真结果表明:采样频率为64MHz,过采样率为32的二阶Σ-Δ调制器的输出1位码流经过该滤波器滤波后,信噪比达到53.8dB;在1.8V工作电压下,功耗约为15mW.版图尺寸0.45mm×0.45mm,能够满足RFID中模数转换器的要求.     

基于FPGA的高效FIR滤波器设计与实现

给出了一种基于FPGA的数字滤波器的设计方法.该方法先通过MATLAB设计出一个具有具体指标FIR滤波器,再对滤波器系数进行处理,使之便于在FPGA中实现,然后采用基于分布式算法和CSD编码的滤波器结构进行设计,从而避免了乘法运算,节约了硬件资源,其流水线的设计方式也提高了运行速度.Matlab和Modelsim防真表明,该设计功能正确,能实现快速滤波     

新型高速CSD编码滤波器及VLSl的实现

通过对BOOTH型乘法器、高速加法器结构和CSD编码滤波器结构的深入研究,开发出一种新型高速CSD编码滤波器结构.采用此结构实现了正交幅度调制器中的一个高速反SINC滤波器,并在ALCATEL 0.35μm CMOS工艺实现.芯片规模7500门,面积1.00mm×0.42mm.     

低功耗可配置CIC滤波器设计

针对超大规模集成电路的发展以及无线射频芯片中带宽可变的需求,提出一种低功耗可配置级联积分梳状(Cascade Integral Comb, CIC)滤波器结构。该结构采用半字节串行算法优化ASIC电路内部位宽,借助多路复用技术减少运算逻辑和存储逻辑单元,并在增益校正部分采用正则有符号数(Canonic Signed Digit, CSD)编码乘法代替全位宽二进制补码乘法,从而实现低功耗目的。信道带宽配置模块选取CIC滤波器采样因子,实现带宽可变功能。通过MATLAB Simulink搭建抽取滤波器模型以验证算法可行性,并采用verilog HDL完成代码设计,仿真结果表明该滤波器可实现2～16倍下采样。基于65 nm COMS标准单元工艺库进行DC综合和ASIC版图设计,与传统CIC滤波器比较,数字电路在功耗方面具有显著优势。     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

一种升余弦成形滤波器的设计

给出一种适用于PHS基带系统中高性能成形滤波器,对比两种实现方法在基带芯片中的性能,利用最少的非零比特位来表示符号数的编码技术即符号数Canonic Sign Digit表示(CSD),采用子结构共享技术改进数字滤波器结构,实现了二进制补码与CSD的转换和系统中升余弦Nyquist成形滤波器的ASIC设计,在SMIC 0.18μm工艺下进行了功能仿真、综合和后仿真。     

一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。     

Design of 2D FIR and IIR Digital Filters with Canonical Signed Digit Coefficients Using Singular Value Decomposition and Genetic Algorithms

In this paper a design approach for two-dimensional finite impulse and infinite impulse response digital filters with canonic signed digit (CSD) coefficients based on singular value decomposition and genetic algorithms (GAs) is presented. The proposed technique uses a new chromosome coding scheme to alleviate the problem encountered by many GAs during crossover and mutation which destroys the CSD property. Examples are given to demonstrate the usefulness of the proposed technique. A comparative study carried out with some of the existing techniques indicates the high throughput property of the proposed technique.     

Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.     

Precise Evaluation of Coaxial to Waveguide Transitions by Means of Inverse Techniques

In this paper, a new two-tier inverse characterization technique for coaxial to waveguide transition evaluation is presented and properly validated. The transition is characterized by estimating its scattering parameters and a cascade procedure is employed in order to compare simulations and measurements during the unterminating procedure. In contrast to other unterminating methods there are no restrictions concerning the number and type of standards and two transitions are simultaneously characterized. Additionally, genetic algorithms and the gradient descent method are used for error minimization during the unterminating stage. The accuracy of this two-tier inverse technique is evaluated as a function of the employed standards and the obtained results are compared to those provided by different well-known calibration algorithms. Results show that it is possible to properly characterize the coaxial to waveguide transition in a very flexible and accurate way.      

A Graphics Processing Unit Accelerated Genetic Algorithm for Affine Invariant Matching of Broken Contours

Past research works have demonstrated matching of fragmented contours can be effectively accomplished with the integration of genetic algorithms and migrant principle. Despite the success, the computation involved in the evaluation of the fitness function is substantial. To overcome this problem, a new formulation on the fitness evaluation targeted for graphics processing unit (GPU) has been developed and presented in this paper. Experimental results reveal that the proposed solution is capable of reducing the matching time while maintaining high success rates.     

Neurogenetic design centering

A new technique for design centering and yield enhancement of devices and circuits is presented. The proposed method uses neural networks for device and/or circuit modeling and genetic algorithms for parametric yield optimization. It uses a Monte Carlo-based method for yield estimation via the neural models (thus consuming less time) and genetic algorithms for efficient design centering. The neurogenetic methodology has been used for design centering of SiGe heterojunction transistors and millimeter-wave voltage controlled oscillators. It results in significant yield enhancement of the SiGe heterojunction bipolar transistors (from 25% to 75%) and voltage controlled oscillators (from 8 % to 85 %). To the best of our knowledge, this method has not been reported previously.     

The Performance Comparisons between the Unconstrained and Constrained Equalization Algorithms

1　IntroductionAdaptivefilteringtechniquesareusedexten sivelyincommunicationapplicationsforchannele qualization,systemidentification ,antennaarrayprocessing,andinterferencecancellation[4] .Theessenceofadaptivefilteringisthatitminimizesthemean squarevalueofanestimationerror,definedasthedifferencebetweenadesiredresponseandtheac tualfilteroutput.Theconventionaladaptivefilter ingalgorithmsincludetheLeastMeanSquares(LMS)algorithm[5] ,theRecursiveLeast Squares(RLS)algorithm[6] ,theSteepestDece…     

E面分支波导耦合器的遗传算法优化设计

介绍了E面分支波导耦合器基于遗传算法的优化设计方法。详细讨论了遗传算法的优化策略和一个四端口5dB五分支波导耦合器设计实例，及该实例的等效网络综合结果和优化策略和一个四端口5dB五分支波导耦合器设计实例，及该实例的等效网络综合结果和优化后的HFSS软件仿真结果。通过比较可以发现，遗传算法优化结果完全满足期望的优化目标，经过优化设计，耦合器的频响特性有了明显改善。     

多个体参与交叉的Pareto多目标遗传算法

Pareto多目标遗传算法是利用Pareto最优的概念发展出的一种求解多目标优化问题的向量优化方法,能够得到Pareto最优解集.由于采用常规的两个体参与交叉的遗传算法,使整个算法耗费在小生境(Niche)算子上的时间太多,导致算法的效率较低.本文发展出多个体参与交叉的Pareto多目标遗传算法,群体中的个体采用真实值表示,使该算法的速度大大提高,同时证明了相应的模式定理,并提出用方差和熵来分析该算法对解群多样性的影响.最后用算例说明了采用多个体参与交叉的Pareto多目标遗传算法与常规算法比较的结果,证明了本文提出算法的优越性.     

Mobility prediction in mobile ad hoc networks using a lightweight genetic algorithm

A mobile ad hoc network is a collection of wireless mobile nodes creating a network without using any existing infrastructure. Much research has been carried out to find out an optimal routing protocol for the successful transmission of data in this network. The main hindrance is the mobility of the network. If the mobility pattern of the network can be predicted, it will help in improving the QoS of the network. This paper discusses a novel approach to mobility prediction using movement history and existing concepts of genetic algorithms, to improve the MANET routing algorithms. The proposed lightweight genetic algorithm performs outlier removal on the basis of heuristics and parent selection using the weighted roulette wheel algorithm. After performing the genetic operations a node to node adjacency matrix is obtained from which the predicted direction of each node is calculated using force directed graphs and vector calculations. The technique proposes a new approach to mobility prediction which does not depend on probabilistic methods and which is completely based on genetic algorithms.