Flash器件中氧化硅/氮化硅/氧化硅的特性

对普遍采用的氧化硅/氮化硅/氧化硅(ONO)三层复合结构介质层的制备工艺及特性进行了研究分析,研究了ONO的漏电特性以及顶氧(top oxide)和底氧(bottom oxide)的厚度对ONO层漏电的影响.结果表明,采用较薄的底氧和较厚的顶氧,既能保证较高的临界电场强度,又能获得较薄的等效氧化层厚度,提高耦合率,降低编程电压.     

非晶硅顶电池中的n型掺杂层对非晶硅/微晶硅叠层太阳电池性能的影响

采用超高频等离子增强化学气相沉积(VHF-PECVD)技术,逐次高速沉积非品硅顶电池及微晶硅底电池,形成pin/pin型非晶硅/微晶硅叠层电池.通常顶电池的n层与底电池的P层均采用微晶硅材料来形成隧穿复合结,然而该叠层电池的光谱响应测试结果表明,顶电池存在着明显的漏电现象.针对该问题作者提出,在顶电池的微品硅n层中引入非晶硅n保护层的方法.实验结果表明,非晶硅n层的引入有效地改善了顶电池漏电的现象;在非晶硅n层的厚度为6nm时,顶电池的漏电现象消失,叠层电池的开路电压由原来的1.27提高到1.33V,填允因子由60%提高剑63%.     

非晶硅顶电池中的n型掺杂层对非晶硅/微晶硅叠层太阳电池性能的影响

采用超高频等离子增强化学气相沉积(VHF-PECVD)技术,逐次高速沉积非品硅顶电池及微晶硅底电池,形成pin/pin型非晶硅/微晶硅叠层电池.通常顶电池的n层与底电池的P层均采用微晶硅材料来形成隧穿复合结,然而该叠层电池的光谱响应测试结果表明,顶电池存在着明显的漏电现象.针对该问题作者提出,在顶电池的微品硅n层中引入非晶硅n保护层的方法.实验结果表明,非晶硅n层的引入有效地改善了顶电池漏电的现象;在非晶硅n层的厚度为6nm时,顶电池的漏电现象消失,叠层电池的开路电压由原来的1.27提高到1.33V,填允因子由60%提高剑63%.     

用于存储器电路的ONO结构特性研究

为研究存储器的多晶间介质采用ONO(Oxide-Nitride-Oxide)结构的基本特性,从ONO叠层的工作原理和它在器件制作中的工艺结构出发,设计了采用ONO结构存储器的模拟实验,对不同工艺条件下的ONO叠层作对比实验,通过ONO叠层的I-V曲线、漏电流、击穿场强和电荷保持特性的测试及分析,研究了不同生长条件对ONO结构的影响程度,获得了最优的ONO叠层制作条件,为存储器的设计和工艺控制提供了参考.     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

新材料显著降低45nm制程的漏电量

采用氧化硅制造晶体管栅介质已有40余年,随着氧化硅被加工得越来越薄,晶体管性能也稳步提高.然而,从90nm到65nm,再到45nm,氧化硅栅介质厚度的缩小也使栅介质的漏电量越来越高,导致了高能耗和不必要的发热.晶体管栅漏电与不断变薄的氧化硅栅介质有关,这一点已成为过去10年来摩尔定律面临的最大技术挑战之一.     

采用TEOS和H_2O源PECVD方法生长氧化硅厚膜

开展了使用 TEOS和 H2 O混合物进行 PECVD生长 Si O2 膜的研究工作 .氧化硅折射率分布在 1.45 3±0 .0 0 1的范围 ,且随偏离中心距离基本不变 .薄膜厚度是中央大 ,边沿薄 ,其厚度相对变化不超过± 1.5 % (5 1mm衬底 ) .利用 TEOS源 PECVD,并结合退火技术 ,摸索出厚膜氧化硅生长工艺 ,已成功地在硅衬底上生长出厚度超过 15 μm氧化硅厚膜 ,可用于制备氧化硅平面波导器件 .     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为4和5nm的n-MOSFETs进行了沟道热载流子应力加速寿命实验,研究了饱和漏电流在热载流子应力下的退化.在饱和漏电流退化特性的基础上提出了电子流量模型,此模型适用于氧化层厚度为4 5nm或更薄的器件.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

不同AlGaN层厚度的AlGaN/GaN高电子迁移率晶体管的静态特性

利用金属有机化合物气相外延技术研究了AlGaN/GaN高电子迁移率晶体管(HEMT)结构的外延生长及器件制作,重点比较了具有不同AlGaN层厚度的HEMT器件的静态特性.实验发现具有较薄AlGaN隔离层的结构表现出较好的器件特性.栅长为1μm的器件获得了650mA/mm的最大饱和电流密度和100mS/mm的最大跨导.     

Polyoxide thinning limitation and superior ONO interpoly dielectricfor nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate     

High-field mobility effects in reoxidized nitrided oxide (ONO)transistors

The high-field mobility behavior of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room temperature and 77 K on both n- an p-channel FETs, for both ONO and conventional SiO ₂ films. While the peak electron mobility is much higher for standard SiO₂, a crossover occurs in the high-field region beyond which ONO transistors exhibit higher mobility. The crossover voltage is reduced at 77 K. Measurements intended to gain further insight into this phenomenon suggest that differences in surface roughness scattering, or the buried-channel nature of an ONO NMOS transistor, are the most likely explanations for the high-field mobility behavior observed     

Characteristics of the NO dielectric film with low pressure chemical vapor deposition in-situ nitridation

We investigated the formation of the thin NO dielectric films by in-situ nitridation of native oxide, and subsequent deposition of silicon nitride in the low pressure chemical vapor deposition systems for the application to the capacitors in high density dynamic random access memory. The native oxide was nitrided at elevated temperatures of 690 or 780°C in the flowing ammonia gas atmosphere, and nitride was deposited by flowing silane gas additionally immediately after the nitridation process. By in-situ nitridation process, we could obtaine 5 and 4.5 nm thick (equivalent oxide thickness) nitride/oxide (NO) dielectric films. These films were characterized to be electrically more reliable than the conventional oxide/nitride/oxide (ONO) films of the same equivalent oxide thickness. The nitrided NO films also showed lower leakage current and higher breakdown voltage than conventional ONO films. We obtained electrically most reliable NO films by loading the wafer at 400°C and nitriding the native oxide at 780°C.     

Insulator investigation on SiC for improved reliability

Significant improved high-temperature reliability of SiC metal-insulator-semiconductor (MIS) devices has been achieved with both thermally grown oxides and by using a stacked dielectric consisting of silicon oxide-nitride-oxide (ONO). Capacitors of p-type 6H-SiC, n-type 6H-SiC and n-type 4H-SiC were fabricated with a variety of insulators. The best performance was accomplished only with insulators incorporating silicon dioxide. A new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxide and the high-quality interface of a wet oxide. MIS field effect transistors (MISFETs) with an ONO gate insulator had surface channel mobilities similar to MISFETs with thermal gate oxides, and demonstrated a lifetime of 10 days at 335°C and 15 V bias. The lifetime of the ONO MISFET was a factor of 100 higher than for devices fabricated with deposited oxides, which had been the prior state of the art for high-temperature MISFETs on SiC     

Thickness Scaling and Reliability Comparison for the Inter-Poly High- κ Dielectrics

In this letter, the inter-poly dielectric (IPD) thickness, scaling, and reliability characteristics of Al₂O₃ and HfO₂ IPDs are studied, which are then compared with conventional oxide/nitride/oxide (ONO) IPD. Regardless of deposition tools, drastic leakage current reduction and reliability improvement have been demonstrated by replacing ONO IPD with high-permittivity (high-kappa) IPDs, which is suitable for mass production applications in the future. Moreover, metal-organic chemical vapor deposition (MOCVD) can be used to further promote dielectric reliability when compared to reactive-sputtering deposition. By using the MOCVD, the charge-to-breakdown (Q_BD) can be significantly improved, in addition to enhanced breakdown voltage and effective breakdown field. Our results clearly demonstrate that high- IPD, particularly deposited by MOCVD, possesses great potential for next-generation stacked-gate Flash memories.     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Long-term electron leakage mechanisms through ONO interpoly dielectric in stacked-gate EEPROM cells

Analyzing the measured shift rate of cell threshold-voltage, we have studied the long-term electron leakage mechanisms through an oxide-nitride-oxide (ONO) interpoly dielectric, which causes reliability problems due to the degradation of the data retention characteristics in the stacked-gate Flash EEPROM devices. The cell threshold-voltage shifts were measured as a function of bake time at various temperatures by the high-temperature accelerated test. Based on the experimental results, a new empirical model was developed and evaluated. It can explain the dominant mechanisms for the spontaneous charge leakage through an ONO interpoly dielectric for the long-term phase. The model clearly shows that cell threshold-voltage shifts during the baking test are caused predominantly by the thermally activated direct-tunneling when electrons, after escaping from the internitride trap-sites near the top oxide of ONO layer by the thermionic emission mechanism, finally tunnel through the thin top oxide to the control gate. This interpretation is strongly supported by the V/sub T/-shift and temperature dependence of the V/sub T/-shift rate, showing that the simulation results are well fit to the experimental data.     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Electrical characteristics of ferroelectric PZT thin films for DRAMapplications

Ferroelectric lead zirconate titanate (PZT) films with as much as 2.5 times the storage capacity of the best reported silicon oxide/nitride/oxide (ONO) stacked dielectrics have been fabricated. A 2000-Å film with an effective SiO₂ thickness of 10 Å is demonstrated. Because of the extremely high dielectric constant (ϵ_r≳>1000), even larger storage capacities can be obtained by scaling the ferroelectric film thickness, whereas the thickness of ONO films is limited by direct tunneling through the film. Electrical conduction in the PZT films studied is ohmic at electric fields below 250 kV/cm and follows an exponential field dependence at higher fields, which is shown to be consistent with a simple model for electronic hopping through the film. Leakage current as low as 9×10^-8 A/cm² at 2.5 V for a 4000-Å film is obtained with the addition of La and Fe to compensate for Pb and O vacancies in the film. Further improvement in both leakage current and time-dependent dielectric breakdown characteristics are necessary to ensure reliable DRAM operation     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.