低功耗可编程吞脉冲计数器设计

介绍了一种基于0.18μm CMOS工艺的频率合成器子电路吞脉冲计数器的设计方法,并对电路功耗进行了优化.仿真结果表明,该计数器可与双模预分频器构成分频比连续变化的可变分频器,系统最高工作频率为7.5GHz,双模预分频器为采用相位切换结构的16/17预分频器,吞脉冲计数器部分最高工作频率为700MHz,电源电压2V,消耗电流小于0.4mA.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

GHz波段跳频锁相环关键技术研究

介绍了一种除低通滤波器片外单片集成锁相环(Phase-Locked Loop,PLL)频率综合器设计.整个设计对压控振荡器、双模预分频器(Dual-Modulus Prescaler,DMP)与电荷泵(Charge Pump,CP)等锁相环关键模块分别作了优化与改进,提高了各项设计性能.压控振荡器(Voltage Controlled Oscillator,VCO)输出最高频率为1.25GHz时相位噪声为-118.43dBc/Hz@1MHz,VCO调谐范围为250MHz.双模预分频器实现了高精度低抖动低功耗设计,双模预分频器分频输出118.3MHz时,峰峰抖动小于20ps而功耗仅3.2mA.     

一种宽分频范围的CMOS可编程分频器设计

设计了一种基于双模预分频的宽范围可编程分频器。对预分频器的逻辑电路进行了改进,提高了最高工作频率,同时,引入输入缓冲级,增加了低频时分频器的输入敏感性。基于Chartered 0.25μm厚栅CMOS工艺,在SpectreRF中仿真,分频器可在50MHz～2.2GHz频率范围正常工作。流片测试结果表明,该分频器可正常工作在作为数字电视调谐芯片本振源的PLL中,对80～900MHz的VCO输出信号,实现256～32767连续分频。     

极小频率分辨率的小数分频4模方案的实现

引言 稳定频率的获得借助于锁相环路。较小频率步进的获得则必须借助小数分频技术。小数分频的实现运用脉冲吞除原理,脉冲吞除的实现运用的是变模程序分频器。即对被分频信号预分频使得在高速分频器中只需采用少量ECL、TTL器件,这里的分频比是可变的,对于双模程序分频器为p/p+1,将分频信号的频率降低p倍。这里p的取值比     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

一种宽带低功耗低相位噪声的双模预分频器

本文设计了应用SCL、TPSC和CMOS静态三种类型的触发器配合工作的新型双模预分频器。与传统使用单一种类型触发器的双模预分频器相比,该双模预分频器更容易获得高速、宽带、低功耗和低相位噪声的性能。为了验证此设计的性能,采用了SMIC 0.18um CMOS 工艺流片实现。在电源电压为1.8V的条件下测试,此双模预分频器的工作频率范围从0.9 GHz 到 3.4 GHz ;当输入信号为 3.4 GHz时,其功耗为2.51mW,相位噪声为-134.78 dBc/Hz @ 1 MHz. 其核心面积为 is 57um*30um。鉴于其良好的性能,可以应用于许多射频系统的频率综合器中,特别在多标准无线通信系统中。     

6GHz新型高速低功耗分频器

高速数字分频器在基于锁相环的时钟产生电路中具有广泛的应用．在典型D触发器的基础上,文中提出了一种可响应6GHz输入时钟的改进型二分频结构,并实现了2-256连续分频的新型吞脉冲多模分频器．新型分频器结构简单并且不需要双模预分频单元,功耗和面积开销大幅度的降低．基于65rimCMOS工艺设计实现了该高速分频器,版图后仿真结果表明,分频器功能正确,且工作于6GHz时功耗不大于1．3mW．     

射频接收机中低抖动双模分频器

对射频接收机中双模分频器的设计和应用进行了研究.提出了一种改进型D-latch以提高双模分频器速度与驱动能力,一种将D-latch与"或"逻辑门集成的结构以降低电路的复杂度.采用TSMC 0.18μm CMOS混合信号工艺实现了用于地面数字电视接收机的除16/17双模分频器.采用0.18μm CMOS标准单元库设计并以与双模分频器同样的工艺实现了可编程吞吐式脉冲分频器.测试结果显示双模分频器的输出抖动小于0.03%,而且能够与可编程吞吐式脉冲分频器良好地配合工作.     

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.     

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with 'OR' logic for dual-modulus operation,the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process.The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.     

A 5-GHz programmable frequency divider in 0.18-μM CMOS technology

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.     

A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 μm CMOS

A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 m standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.     

一种600MHzECL高速程控分频器的设计

介绍一种ＥＣＬ高速程控分频器的逻辑设计、电路设计及研制结果。该电路的分频比为１２－７５之间任意连续可变的自然数，最高工作频率达６００ＭＨｚ可广泛用于雷达，通讯和频率合成器等领域。     

Low Power 1 GHz Frequency Synthesizer LSI's

To realize a low-power low-cost highly-reliable frequency synthesizer for a 1 GHz band radio, a bipolar presealer IC, and a CMOS LSI, consisting of a programmable counter, phase frequency comparator, and fixed divider, have been developed. The PLL synthesizer principle, using a pulse swallow counter, has been adopted for 1 GHz direct programmable count down. Adopting an advanced bipolar process and a diode AND circuit for the dual modulus presealer IC, high frequency operation at 1 GHz and 150 mW low power dissipation have been achieved simultaneously. To reduce the loop delay in the CMOS programmable counter, which limits the operating frequency, a new circuit configuration for the programmable counter and pulse swallow counter is adopted. As a result, 1 GHz frequency synthesizer LSI's have been developed with 150 mW low power dissipation for the presealer IC and 18 mW low power dissipation for CMOS LSI.