共查询到17条相似文献,搜索用时 78 毫秒
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LDPC在DVB-S2中的应用 总被引:2,自引:1,他引:2
介绍了LDPC码,并基于DVB-S2中LDPC码分析了该类码的构造、编码及解码原理,同时给出DVB-S2中LDPC码的结构及仿真结果. 相似文献
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随着VLSI技术的发展,LDPC(Low Density Parity Check)码被确定为下一代数字卫星电视标准(DVB-S2)的信道编码方案。文中针对DVB—S2标准,分析了LDPC码的结构特点,给出了LDPC译码改进算法,从而降低了其实现的复杂度。同时通过算法仿真,验证了LDPC改进算法在低信噪比条件下的卓越性能和高速率的数据处理速度。 相似文献
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LDPC码性能非常逼近香农极限且实现复杂度低,具有很强的纠错抗干扰能力,几乎适用于所有信道。在此采用DVB-S2标准中LDPC码的构造和编码方案,重点研究了LDPC码的译码原理,并将其用于加性高斯白噪声信道(AWGN Channel)图像的传输中。仿真结果表明在非规则LDPC码在低信噪比情况下,能为图像传输带来显著性能提高,且系统复杂度低,译码时延短。 相似文献
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DVB-S2标准低密度奇偶校验码(LDPC)译码器在深空通信中面临着低复杂度、高灵活性及普适性方面的迫切需求。通过对LDPC译码算法中量化结构的研究,提出一种动态自适应量化结构的设计方法。该方法在常规均匀硬件量化的基础上,提出了修正化Min-Sum译码算法中的数据信息初始化及迭代译码的动态自适应量化结构,解决了DVB-S2标准LDPC码译码时存在的校验节点运算与变量节点运算之间的复杂度不平衡的问题,并由此提高了译码器的译码性能。实验证明,以DVB-S2标准LDPC码中码长为16 200,码率为1/2的为例,提供动态自适应量化结构与常规的均匀量化结构相比,节省硬件资源为4%。此外,动态自适应量化结构支持动态可配置功能,保证了DVB-S2标准LDPC译码器的灵活性及普适性。 相似文献
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DVB-S2标准IRA-LDPC译码算法研究与改进 总被引:4,自引:4,他引:0
首先对DVB-S2标准LDPC码编码原理、IRA码以及校验矩阵的特征进行了分析,接着对该标准中LDPC码的Tanner图参数进行了总结,然后对不同的译码算法从性能和复杂度方面进行了比较,并且对不同迭代次数时LDPC码的判决信息的分布进行了分析,最后对各种译码算法的性能和复杂度进行了总结.仿真结果表明,SPA译码算法性能最优但是复杂度最大,MinSum算法的复杂度最低但是性能最差,而改进的MinSum算法则在复杂度和性能方面是前面两种算法的折中,对实际工程的应用有较强的借鉴作用. 相似文献
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Albert Abelló Damien Roque Jean-Marie Freixe Sébastien Mallier 《Analog Integrated Circuits and Signal Processing》2017,91(2):267-276
In the framework of digital video broadcasting by satellite-second generation (DVB-S2), we analyze a faster-than-Nyquist (FTN) system based on turbo equalization and low-density parity-check (LDPC) codes. Truncated maximum a posteriori and minimum mean square error equalizers provide a reduced-complexity implementation of the FTN system. On the other hand, LDPC codes allow us to demonstrate attractive performance results over an additive white Gaussian noise channel while increasing spectral efficiency beyond the Nyquist rate and keeping a complexity comparable to that of a current DVB-S2 modem. 相似文献
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一种新的终止LDPC迭代译码算法 总被引:1,自引:1,他引:0
在传统的卫星广播系统中,信道纠错通常采用BCH码级联LDPC码的方案以达到良好的误码率性能,例如DVB-S2系统。作为内码的LDPC码通常采用迭代译码,且迭代次数较高才能实现比较好的系统性能。借助BCH级联LDPC的结构,文中提出了将BCH检错嵌套进LDPC每一次迭代译码过程中的新的迭代译码结构。仿真结果表明,新算法以较低的BCH码检错运算复杂度换取了LDPC码迭代次数的明显下降,从而极大降低了迭代译码总体复杂度和译码时延,且整体纠错性能与原始LDPC译码后BCH纠错的算法相比基本保持不变。 相似文献
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Papaharalabos S. Papaleo M. Mathiopoulos P.T. Neri M. Vanelli-Coralli A. Corazza G.E. 《Broadcasting, IEEE Transactions on》2008,54(1):120-126
Broadband satellite services to fixed terminals are currently offered in the forward link by the 2nd generation (2G) digital video broadcasting satellite (DVB-S2) standard. For this standard the use of powerful low-density parity-check (LDPC) error correcting codes has been adopted performing within approximately 1 dB from the Shannon capacity limit. This paper studies and compares for the first time in a systematic manner different approximation methods used in check node update computation of DVB-S2 LDPC decoding with the aim of reducing computational complexity. Various performance evaluation results are presented for a wide range of DVB-S2 parameters, such as LDPC codeword size, coding rate, modulation format and including several decoding algorithms. It is shown that the proposed check node update approximations have a robust behavior, i.e. the resulting performance is quite independent of the DVB-S2 modulation and coding parameters. It is further shown that these approximations perform very close to the optimal sum-product algorithm (SPA) in degradation, which is less than 0.2 dB. Despite this small degradation, the reduction in computational complexity compared to the optimal SPA is significant and can be as high as 40% in computational time savings. 相似文献
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Implementation of a Flexible LDPC Decoder 总被引:1,自引:0,他引:1
Masera G. Quaglio F. Vacca F. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(6):542-546
Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated. 相似文献
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Stefan Gr?nroos Kristian Nybom Jerker Bj?rkqvist 《Analog Integrated Circuits and Signal Processing》2012,73(2):583-595
The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard??at the high data rates required for television broadcasting??possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs. 相似文献