Reusing existing resources for testing a multi-processor system-on-chip

In this article, we propose a test strategy for a multi-processor system-on-chip and model the test time for distributed Intellectual Property (IP) cores. The proposed test methodology uses the existing on-chip resources, IP cores and network elements in network-on-chip. The use of embedded IP cores as a built- in self-test (BIST) module completes the test much faster than an external test and provides flexibility in the test program. Moreover, the reuse of the existing network resources as a test media eliminates additional test access mechanism (TAM) wires in the design and increases test parallelism, reducing the area and test time. Based on the proposed test methodology, we evaluate the test time for distributed IP cores. First, we define the model for a distributed IP core with four parameters in the context of test purposes. Next, the required test time is driven. Finally, we show the characteristics of IP cores for a parallel testing that provides useful information for the test scheduling.     

实现测试复用的SOC设计中的测试结构

在系统芯片SOC(system on a chip)设计中实现IP核测试复用的芯片测试结构一般包含两个部分：1)用于传送测试激励和测试响应的片上测试访问机制TAM;2)实现测试控制的芯片测试控制器。文章分析了基于测试总线的芯片测试结构,详细阐述了SOC设计中测试调度的概念,给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。     

基于TCL的网络自动化测试系统设计

网络自动化测试系统是从网络测试的需求出发对传统的手动测试进行改进。通过采用分布式IP网络测试架构,设计了一套基于TCL的自动化测试平台,能较好地完成对待测IP网络性能进行全面综合的评价。测试例脚本将网络的性能、功能以及IP协议的测试配置流程代码化,在搭建好的测试平台上执行测试,实现了网络测试的自动化。结合＂指定VLAN...     

基于“云”的LTEeNB自动化测试系统解决方案

介绍了一种基于＂云＂的LTEeNB测试系统解决方案,以云计算为指导思想,配合LTE基站测试系统各平台结构,提出了一种高效的测试方案。该方案包含了LTE基站测试中子系统测试（SST）、调制板集成测试（MIT）、系统测试（ST）以及端到端测试（MTMT）等各类型。本文在传统测试模式基础上,提出了平台和资源共享测试机制;提供...     

面向TPS架构的混合电路测试系统设计

面向测试程序集（TPS）软件架构是通用自动测试系统的发展方向,而建立统一的测试系统模型是测试系统中资源管理与配置的关键。提出了一种基于TPS的自动测试系统建模方案及实现机制,利用关系型数据库建立包括仪器仪表资源自动配置、被测件管理、测试底版通信控制的自动测试系统模型。基于VC6.0平台,在测试主程序与仪器仪表控制、与测试底版之间建立引擎,实现资源的自动选择和配置,解决了测试程序对仪器仪表的依赖问题及测试底版的通用性问题。该方案已经成功应用于某出口三型雷达综合电路集成测试系统中。     

并行测试的一种新策略--测试段划分

由于测试响应观察及测试 置入只占用了测试时间的一部分,我们采用测试段划分策略来进一步利用测试调度资源。这样,原来在测试设计调度过程中冲突的子电路对采用测试段划分策略以后可能只是部分冲突了。文中提出了一种新的测试调度算法。该算法通过记录以往的冲突信息,提高了测试调度调度最优解的搜索效率。     

Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t_RAS wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed     

A new maximal diagnosis algorithm for interconnect test

Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-level test is performed for repair, noticing the faulty position is an essential element of any interconnect test. Generally, the interconnect test algorithms that need a short test time cannot perform the complete diagnosis and the algorithms that perform the complete diagnosis need a lengthy test time. To overcome this problem, a new interconnect test algorithm is developed. The new algorithm can provide the complete diagnosis of all faults with a shorter test time compared to the previous algorithms.     

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.     

Enabling Remote Testing: Embedded Test Controller and Mixed-signal Test Architecture

Remote testing requires embedded test infrastructure, consisting of communication, test control and test access. This article presents an embedded test solution for a low-frequency audio board. Supporting analog testing, the solution consists of a measurement and calculation method for passive component characterization, analog test bus solution and an embedded test controller for controlling embedded tests and providing test stimuli. Moreover, the solution, which supports the presented test plan, was compared to a test plan supporting traditional testing. It was found that the embedded test solution provided a 29% test coverage of the audio board components and substituted flying probe testing included in the traditional test plan. Besides such benefits as improved fault diagnostics and lower manufacturing costs, the paper also discusses the drawbacks of the presented solution, including reduced measurement accuracy. This paper also presents a correction to a previously presented passive component measurement and calculation method.     

单比特频数检测和块内频数检测的快速实现研究

随机序列在密码技术中占有非常重要的地位,随机性检测利用概率统计的方法对随机序列的随机性进行分析测试。美国国家标准与技术研究院(NIST)和我国国家密码管理局都发布了各自的随机性检测规范,二者都将单比特频数检测和块内频数检测作为其检测项。研究了单比特频数检测和块内频数检测的快速实现,提出了三种新的快速实现算法。这三种算法可以使单比特频数检测、块内频数检测和两种检测综合实现的速度分别提升29.2倍、15.5倍和32.8倍。     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

嵌入式采集系统的应用研究

本文以某型雷达试飞为背景,设计搭建了嵌入式采集系统测试方案,用于采集多路ARINC429总线及开关量信号,并以惯导、被试设备仿真系统为信号源,对嵌入式采集系统采集记录功能进行了仿真测试,并在雷达试飞中进行飞行验证,通过仿真测试和飞行验证,嵌入式采集系统能够完成机载设备试飞数据采集记录。     

自动测试系统通用测试平台技术研究

随着电子设备测试需求的增高,越来越多的自动测试系统投入到实际应用中,由此带来了多种电子设备测试系统兼容的问题,并造成了一定的资源浪费,因此需要有一种通用的自动测试系统通用测试平台来解决这种问题.本文通过对国外自动测试系统典型通用测试平台的研究提出了一种可灵活二次开发自动测试系统通用平台设计思想,并在某型号航电设备测试系统中得到了较好的应用.     

电子装备通用测试体系关键技术研究

为解决电子装备自动测试系统的数量多,功能重复等问题,提出了电子装备通用测试平台,通过分析多种总线结构、测试硬件和驱动体系的核心指标与技术特征,借鉴分层思想设计通用型体系架构,以多种测试仪器为基础,利用多层次的驱动体系屏蔽混合总线差异,将测试程序与测试仪器分离,实现了只需更换测试仪器和配置对应的驱动,便可置换底层仪器,使通用测试平台具备较强的扩展能力,覆盖更多测试需求,有效降低测试系统的数量。     

宇航元器件搭载试验研究与实践

元器件搭载是国内外航天器,特别是新技术试验卫星中的一类重要试验项目,也是推动元器件成熟和宇航应用的重要手段。从元器件搭载试验验证体制、天地联合验证方法、试验组织、试验结论发布和应用等方面,对元器件搭载试验提出了总体策略,对搭载试验任务内容和要求进行了分析,总结了元器件搭载试验的实践。研究工作对我国宇航元器件搭载试验相关工作具有较高的参考价值。     

基于测试路径集运算的类回归测试策略研究

从基于状态的类测试策略出发,提出了一种基于测试路径集运算的类回归测试策略。该策略将回归测试作为一个连续的过程以测试路径为运算对象。对已修改的类重新生成测试集,通过与原测试集进行简单的集合运算从中选取可用于回归测试的测试用例。研究表明,该策略能充分利用历史测试数据,降低运算复杂度,提高回归测试的效率。     

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test sets that are compatible with the test responses of their individual preceding cores. This part can be removed from their original test sets, and (2) the test sets that none of the test vectors from them are compatible with the test responses of their individual preceding cores. On hardware implementation, only a couple of 2-1 MUXs are needed. The algorithms for reordering the sequences of core-under-tests and those of the test vectors for each corresponding core are outlined for optimal test compression results. It needs neither coder nor decoder, thus saving hardware overhead. Power-constrained SoC core test pipelining consumes less test application time. Hierarchical clustering-based SoC test scheduling can be implemented easily, and the hardware overhead is negligible. Experimental results on benchmark ISCAS 89 demonstrate that our method achieves significant improvement of test time and less ATE requirement over the previous methods, and it does not discount the fault coverage of each test set, moreover, the fault coverage for some test sets is improved instead.