Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

GaN-based optoelectronic devices on sapphire and Si substrates

A recessed gate AlGaN/GaN high-electron mobility transistor (HEMT) on sapphire (0 0 0 1), a GaN metal-semiconductor field-effect transistor (MESFET) and an InGaN multiple-quantum well green light-emitting diode (LED) on Si (1 1 1) substrates have been grown by metalorganic chemical vapor deposition. The AlGaN/GaN intermediate layers have been used for the growth of GaN MESFET and LED on Si substrates. A two-dimensional electron gas mobility as high as 9260 cm²/V s with a sheet carrier density of 4.8×10¹² cm⁻² was measured at 4.6 K for the AlGaN/GaN heterostructure on the sapphire substrate. The recessed gate device on sapphire showed a maximum extrinsic transconductance of 146 mS/mm and a drain–source current of 900 mA/mm for the AlGaN/GaN HEMT with a gate length of 2.1 μm at 25°C. The GaN MESFET on Si showed a maximum extrinsic transconductance of 25 mS/mm and a drain–source current of 169 mA/mm with a complete pinch-off for the 2.5-μm-gate length. The LED on Si exhibited an operating voltage of 18 V, a series resistance of 300 Ω, an optical output power of 10 μW and a peak emission wavelength of 505 nm with a full-width at half-maximum of 33 nm at 20 mA drive current.     

Role of Schottky barrier height at source/drain contact for electrical improvement in high carrier concentration amorphous InGaZnO thin film transistors

We report the fabrication of bottom-gate thin film transistors (TFTs) at various carrier concentrations of an amorphous InGaZnO (a-IGZO) active layer from ~10¹⁶ to ~10¹⁹ cm⁻³, which exceeds the limit of the concentration range for a conventional active layer in a TFT. Using the Schottky TFTs configuration yielded high TFT performance with saturation mobility (μ_sat), threshold voltage (V_TH), and on off current ratio (I_ON/I_OFF) of 16.1 cm²/V s, −1.22 V, and 1.3×10⁸, respectively, at the highest carrier concentration active layer of 10¹⁹ cm⁻³. Other carrier concentrations (<10¹⁹ cm⁻³) of IGZO resulted in a decrease of its work function and increase in activation energy, which changes the source/drain (S/D) contact with the active layer behavior from Schottky to quasi Ohmic, resulting in achieving conventional TFT. Hence, we successfully manipulate the barrier height between the active layer and the S/D contact by changing the carrier concentration of the active layer. Since the performance of this Schottky type TFT yielded favorable results, it is feasible to explore other high carrier concentration ternary and quaternary materials as active layers.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport

A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si_1-yC_y) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of Si_1-yC_y in the S/D regions. The carbon mole fraction incorporated is 0.013. Lattice mismatch of ~0.56% between Si _0.987C_0.013 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron-mobility enhancement. The conduction-band offset DeltaE_c between the Si_0.987 C_0.013 source and the strained Si channel could also contribute to an increased electron injection velocity nu_inj from the source. Implementation of the Si_0.987 C_0.013 S/D regions for n-MOSFET provides significant drive current I_Dsat enhancement of up to 50% at a gate length of 50 nm     

The separation of generation lifetimes of Si and SiGe using capacitance-transient measurements on MOS capacitors formed by plasma anodisation of Si:Si0.9Ge0.1:Si substrates

A simple technique leading to the measurement of minority carrier lifetimes of UHV compatible LPCVD Si and SiGe by C–t depth profiling of Metal:Oxide:Si:SiGe:Si structures is reported. A high quality gate oxide is realised by low temperature (<100°C) plasma anodisation thereby reducing any oxidation effects on the underlying epitaxial layer quality. Capacitance response times were observed for an impurity concentration of 2.5×10¹⁷ cm⁻³, giving rise to generation lifetimes of the Si and Si_0.9Ge_0.1 of >0.55 and 2.6 μs respectively, reflective of very high quality epitaxial semiconductor material.     

Temperature dependent IDS-VGS characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si(110) substrate

在Si(110)衬底上制备了Ge源n型Si沟道隧穿场效应晶体管（TFET）。本文研究了温度对Ge源Si TFET器件的电学性能的影响。温度相关性研究显示器件漏电流主要由漏区的Shockley - Read - Hall (SRH) 产生于复合电流决定。器件开态电流随温度升高而增加,这是因为温度升高材料禁带宽度减小,隧穿几率增大。界面缺陷引起的隧穿电流的亚阈值摆幅随温度升高而变差,但是带间隧穿电流的亚阈值摆幅不随温度变化而变化。     

Remote plasma nitridation, deuterium anneal and pocket implant effects on NMOS hot carrier reliability

There are several advanced processes which are being actively studied as candidates for sub-0.25 μm technology. This paper studies the effects on NMOS hot carrier reliability from remote plasma nitrided oxide (RPNO), deuterium anneal and pocket implant. It is found that RPNO will not affect the SiO₂/Si interface. The hot carrier reliability is better for the same device channel current. This is due to making the effective oxide thickness thinner and achieving the same drive current with longer channel length. The deuterium anneal can improve the hot carrier reliability, even with nitride sidewall, if proper annealing is done. While the pocket implant can reduce short channel effects, the hot carrier lifetime is degraded unless optimization is done.     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

Origin of 1/f noise in lateral PNP bipolar transistors

1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220<T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source S_IB has two dominant components. One is S_IBE that is between the base and the emitter, in parallel with r_π. The other is S_IBC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted S_IB exhibited a near square law dependence on base current I_B. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.     

Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

p‐CuO/n‐Si heterojunction solar cells with high open circuit voltage and photocurrent through interfacial engineering

Heterojunction solar cells of p‐type cupric oxide (CuO) and n‐type silicon (Si), p‐CuO/n‐Si, have been fabricated using conventional sputter and rapid thermal annealing techniques. Photovoltaic properties with an open‐circuit voltage (V_oc) of 380 mV, short circuit current (J_sc) of 1.2 mA/cm², and a photocurrent of 2.9 mA/cm² were observed for the solar cell annealed at 300 °C for 1 min. When the annealing duration was increased, the photocurrent increased, but the V_oc was found to reduce because of the degradation of interface quality. An improvement in the V_oc resulting to a record value of 509 mV and J_sc of 4 mA/cm² with a high photocurrent of ~12 mA/cm² was achieved through interface engineering and controlling the phase transformation of CuO film. X‐ray diffraction, X‐ray photoelectron spectroscopy, and high‐resolution transmission electron microscopy analysis have been used to investigate the interface properties and crystal quality of sputter‐deposited CuO thin film. The improvement in V_oc is mainly due to the enhancement of crystal quality of CuO thin film and interface properties between p‐CuO and n‐Si substrate. The enhancement of photocurrent is found to be due to the reduction of carrier recombination rate as revealed by transient photovoltage spectroscopy analysis. Copyright © 2014 John Wiley & Sons, Ltd.     

Distribution of hydrogen in silicon and silicon carbide following high-temperature proton irradiation

The distribution of hydrogen in Si and SiC following high-temperature proton irradiation (T _irr=20–700 °C) is studied by secondary-ion mass spectrometry. It is shown that the hydrogen concentration profile in SiC depends weakly on irradiation temperature. In Si appreciable alteration of the concentration profile is observed already at T _irr⋍300 °C, and the profile completely loses its concentration gradient at T _irr⋍700 °C. Fiz. Tekh. Poluprovodn. 33, 1409–1410 (December 1999)     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

Enhanced infrared transmission of GZO film by rapid thermal annealing for Si thin film solar cells

Ga doped ZnO (GZO) films prepared by sputtering at room temperature were rapid thermal annealed (RTA) at elevated temperatures. With increasing annealing temperature up to 570°C, film transmission enhanced significantly over wide spectral range especially in infrared region. Hall effect measurements revealed that carrier density decreased from ∼8 × 10²⁰ to ∼ 3 × 10²⁰ cm⁻³ while carrier mobility increased from ∼15 to ∼28 cm²/Vs after the annealing, and consequently low film resistivity was preserved. Hydrogenated microcrystalline Si (µc‐Si:H) and microcrystalline Si_1‐xGe_x (µc‐Si_1‐xGe_x:H, x = 0.1) thin film solar cells fabricated on textured RTA‐treated GZO substrates demonstrated strong enhancement in short‐circuit current density due to improved spectral response, exhibiting quite high conversion efficiencies of 9.5% and 8.2% for µc‐Si:H and µc‐Si_0.9Ge_0.1:H solar cells, respectively. Copyright © 2011 John Wiley & Sons, Ltd.     

Metalorganic chemical vapor deposition of silver thin films for future interconnects by direct liquid injection system

Deposition of Ag films by direct liquid injection-metal organic chemical vapor deposition (DLI-MOCVD) was chosen because this preparation method allows precise control of precursor flow and prevents early decomposition of the precursor as compared to the bubbler-delivery. Silver(I)-2,2-dimethyl-6,6,7,7,8,8,8-heptafluoro-3,5-octanedionato-triethylphosphine [Ag(fod)(PEt₃)] as the precursor for Ag CVD was studied, which is liquid at 30 °C. Ag films were grown on different substrates of SiO₂/Si and TiN/Si. Argon and nitrogen/hydrogen carrier gas was used in a cold wall reactor at a pressure of 50–500 Pa with deposition temperature ranging between 220 °C and 350 °C. Ag films deposited on a TiN/Si diffusion barrier layer have favorable properties over films deposited on SiO₂/Si substrate. At lower temperature (220 °C), film growth is essentially reaction-limited on SiO₂ substrate. Significant dependence of the surface morphology on the deposition conditions exists in our experiments. According to XPS analysis pure Ag films are deposited by DLI-MOCVD at 250 °C by using argon as carrier gas.