面向多功能模拟信号处理的开关电流型可重构模拟电路研究

现有的离散时间型可重构模拟电路采用开关电容技术,存在功能有限、带宽低、与数字CMOS工艺不兼容等问题.本文提出了一种基于电流模取样数据技术的可重构模拟电路,能够与数字CMOS工艺技术兼容.设计了细粒度开关电流型可重构模拟单元,设计了面向开关电流型CAB互连的可编程网络结构.在4×2规模的可重构模拟阵列上,重构实现了三个...     

基于可重构核的FPGA电路设计

电路系统的自适应性、紧凑性和低成本 ,促进了在嵌入式系统中软硬件的协同设计。在线可重构FPGA不仅可以满足这一要求 ,而且在可编程专用电路系统设计的验证及可靠性等方面有着良好的应用 ,文中介绍了可重构 FPGA的实现结构及评估方法 ,提出以线性矢量表征可重构 FPGA及其可重构核的研究模型 ,以及基于可重构核的模块化设计 ,认为面向分类的专用类可重构 FPGA应当是现阶段可重构 FPGA的研究主题。     

采用遗传算法的一种可重构ANN的电路设计

提出了一种新型的 sigm oid函数发生器 .它不仅简单、快速 ,与理想 sigm oid函数的拟合程度好 ,而且可实现阈值和增益因子的编程 ,因而有很大的应用范围和良好的应用前景 .设计了神经元以及 Gilbert乘法器、数字存储器、 D/ A转换器等神经网络的基本单元 .说明了遗传算法 (GA)作为人工神经网络 (ANN)学习算法的有利因素 .利用上述电路 ,采用 GA,设计了可重构 ANN.对各单元电路和整个 ANN都用标准 1.2 μm CMOS工艺的第 47级模型进行了 HSPICE模拟 .结果表明它们的功能正确、性能优良 .     

面向扩频通信的可重构阵列电路研究

传统的可重构电路主要由细粒度数据处理单元组成,但是其实现的运算功能单一,且布线复杂,限制了可重构SoC电路的通用性和灵活性.针对以上问题,根据通信领域基带信号处理的运算特点,设计了一种新型可重构阵列电路,可作为运算模块嵌入可重构SoC,此阵列由粗粒度数据处理单元构成的细胞互联组成.针对基带信号数据位宽多样的特点,细胞可重构实现多种算子.通过在阵列中每个细胞内部都嵌入独立配置存储器,采用并行数据配置电路的方式,以降低阵列的重构时间开销,实现整个阵列的快速重构.以伪码捕获为例,对设计的电路进行仿真.结果显示,设计的结构布线方法简单、通用性及灵活性强.     

兼容多标准的高效运动补偿新结构

为有效解决运动补偿的多标准兼容问题,该文提出了一种改进的适用于多标准运动补偿的新插值算法结构,新插值算法基于文中提出的RL(Rounding Last)策略和DTS(Diagonal Two Step)策略,其采用一种统一的两步插值结构有效地兼容了各标准中亮度分量和色度分量的插值。基于新算法,设计实现了一种可重构的多标准运动补偿硬件电路,该电路采用了基于可变块大小的运动补偿结构。实现结果表明,与JM8.4中基于44固定块大小的运动补偿结构相比,所设计的电路使得带宽需求降低了27%~50%,平均单次访问外部存储器的突发长度提高了1.22~2.25倍;电路在125 MHz工作频率下可满足全高清1080 p (19201080) 30帧/s的实时解码需求。     

可重构天线的研究现状与发展趋势

可重构天线作为一种新型的天线,与传统天线相比具有尺寸小、重量轻、利于实现分集等优点和广阔的发展前景.回顾了可重构天线的发展历程,总结了近年来国内外关于可重构天线的最新研究成果,并从可重构天线的功能、使用的关键器件、设计方法与电路特点等方面对其研究现状进行了深入分析.从多个角度给出了可重构天线的分类与总结,并就可重构天线的设计方法与电路特点进行详细论述和举例说明.最后对可重构天线的发展趋势进行了展望.     

计算机软硬件通信共享存储可重构的优化实现

随着计算机可重构器件的飞速发展以及迅速普及,其内部存储内容可以实现全面共享的可重构计算机软硬件通信已经隧慢地变成世界计算机领域所瞩目的一个问题。由于可重构器件不单单具备硬件电路所拥有的超高计算效率,还可以与此同时具备可进行多次分段编程等硬件电路所不具备的特点,硬件任务以及软件任务近似相等的这一概念逐渐在计算机系统设计的过程中普及开来,共享存储可以以比较灵活的方式来进行一些十分复杂缜密的大型运算工作,并且还打破了常规在设计的过程中将计算机的软硬件协同设计模块进行了大型的修改,这为计算机领域带来了十分巨大的改变。     

基于动态可重构的FFT处理器的设计与实现

提出了一种基于局部动态可重构(DPR)的新型可重构FFT处理器.相比传统的FFT设计,该设计方法在重构时间上得到了很大改进,同时,处理器能够动态地添加或移除重构单元.采用新颖的FFT控制算法,使得可重构部分面积很小.该处理器结构在Xilinx Viirtex2p系列FPGA上进行了综合及后仿真.较之Xilinx IPcore,其运算效率明显提高,而且还实现了IP核所不具备的动态可重构性.     

基于FPGA的动态可重构系统设计与实现

近年来,随着计算机技术的发展,尤其是现场可编程门阵列FPGA的出现,使实时电路重构成为研究热点.基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用.介绍FPGA可重构技术的分类以及动态可重构技术的原理,并在此基础之上选取Virtex-4系列FPGA给出一种动态重构的应用以及具体实现,即通过微处理器(ARM)结合多个FPGA,并采用一种新的边界扫描链方法对多个FPGA进行配置,从而实现局部动态可重构.这种实现方法具有较强通用性和适于模块化设计等优点.     

可编程模拟器件在接收机动态可重构结构中的应用设计

为进一步提高接收机的动态可重构性能，对基于可编程模拟器件的接收机前端结构进行了优化设计，并给出了具体的设计方案，证明了接收机前端动态可重构的可行性。     

Current follower based reconfigurable integrator/differentiator circuits with passive and active components׳ reuse

Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.     

A simple structure wavelet transform circuit employing function link neural networks and SI filters

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

任意阶CCCII-C多功能滤波器的设计

提出了一种基于电流控制传送器(CCCII)任意阶多功能滤波器的设计方法。该方法导出的滤波器具有最少的元件,n阶滤波器仅需n个CCCIIs和n个电容,且所有的电容均接地,便于集成且与VLSI工艺兼容。完成了2阶多功能滤波器和6阶带通滤波器的PSpice仿真,理论分析和计算机仿真表明所提电路方案正确可行。     

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35 μm CMOS is presented.The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF).The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications.In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide-10 to +40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA,and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.     

Current mode filters with reduced complexity using a single EX-CCCII

In this paper an active element Extra-X current controlled conveyor (EX-CCCII) is used to reduce the complexity of some existing circuits. Two second-order current-mode biquadratic filter circuits are proposed, each using a single active element and two grounded capacitors. The first circuit is three input single output (TISO) and the second one is single input three outputs (SITO) biquadratic filter. The First circuit can realize all the standard filter transfer functions, while the second circuit can realize LP, BP and HP responses. The study of non-idealities and parasitics of the active element and their effects on transfer functions is carried out. The new circuits are found to be simpler than the earlier ones in terms of number of transistors. The functionality of the proposed biquadratic filters is verified through detailed PSPICE simulations using 0.25 µm TSMC CMOS technology parameters.     

Fault Detection of Analog Circuits Using Network Parameters

A new method to detect component faults in analog circuits is proposed in this paper. Network parameters like driving point impedance, transfer impedance, voltage gain and current gain are used to detect component faults in analog circuits as these network parameters are sensitive to the components of the circuit. Using montecarlo simulation each component of the circuit is varied within its tolerance limit and the minimum and the maximum values of each network parameter are found for fault free circuit. At the time of testing, the network parameters are found for the injected fault and if any one or more network parameters is exceeding its predetermined bound limits then the circuit is confirmed faulty. The proposed method is validated through second order Sallenkey band pass filter and fourth order Chebyshev low pass filter circuits. Numerical results are presented to clarify the proposed method and prove its efficiency.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.