部分耗尽型SOI CMOS模拟电路设计研究

介绍了部分耗尽型SOI MOS器件浮体状态下的Kink效应及对模拟电路的影响.阐述了4种常用体接触方式及其他消除部分耗尽型SOI MOS器件Kink效应的工艺方法,同时给出了部分耗尽型SOIMOSFET工作在浮体状态下时模拟电路的设计方法.     

SOI—NMOS场效应晶体管的Kink特性分析

本文研究了在室温(RT)、液氮温度(LN)和液氮温度(LHe)下的SOI-NMOS场效应晶体管的电流—电压特性。研究的器件制作在二氧化硅上的经激光退火后的多晶硅薄膜体上。结果表明室温下带有薄膜引出端的晶体管的I_D—V_D特性曲线的Kink形状和液氦下观测到的N-MOS场效应晶体管的Kink形状很类似。实验还表明Kink大小是液氮下比室温下大、液氦下比液氮下的大。应用电容效应,低温下载流子“冻结”机制和不同偏压下载流子产生和复合的物理过程分析可以相应地解释不同温度下Kink效应。     

SOI MOSFET器件X射线总剂量效应研究

研究了以10keV X射线为辐照源对注氧隔离(SIMOX)SOI MOSFET器件进行辐照的总剂量效应.采用ARACOR 10keV X射线对埋氧层加固样品与未加固的对比样品在开态和传输门态两种辐照偏置下进行辐照,分析了器件的特性曲线,并计算了SOI MOS器件前栅与寄生背栅晶体管辐照前后的阈值电压的漂移.实验结果表明,加固样品的抗辐射性能优越,且不同的辐照偏置对SOI MOSFET器件的辐照效应产生不同的影响.     

PDSOI体源连接环形栅nMOS特性研究

提出了一种基于部分耗尽绝缘体上硅的体源连接环形栅nMOS器件,并讨论了相应的工艺技术和工作机理。采用体源连接环形栅器件结构,有效地抑制了浮体环形栅器件中存在的浮体效应和寄生双极晶体管效应,使器件性能得到很大的提高。消除了浮体环形栅器件的反常亚阈值斜率和Kink效应,DIBL从120.7mV/V降低到3.45mV/V,关态击穿电压从4.8V提高到12.1V。最后指出,体源连接环形栅器件非常适合于抗辐照加固等应用领域。     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si).     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si).     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上，提出了提高SOI器件和电路性能的技术途径. 体接触是防止浮体效应的最好方法；正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要；SOI器件栅电极的选取严重影响器件的性能； 源区的浅结有助于减小寄生npn双极晶体管的电流增益；而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用. 研究发现，采用综合加固技术的nMOS器件，抗总剂量的水平可达1E6rad(Si).     

SOI横向双晶体管结构研究

本文首先概括地介绍了体硅、SOI纵向双极晶体管和横向双极晶体管的各自特点，并简要地阐述了SOI横向双极晶体管的发展；其次，对各种SOI横向双极晶体管的结构与性能进行了分析研究；最后，我们认为SOI横向双极晶体管是一种比较理想的双极器件，不失为SOI／BiCMOS的理想选择。     

SOI铁电负电容晶体管亚阈值特性研究

随着微电子技术进入纳米领域,功耗成为制约技术发展的主要因素,因此,低功耗器件成为半导体器件领域的研究热点。负电容场效应晶体管基于铁电材料的负电容效应可有效地降低器件的亚阈值摆幅,从而降低器件的功耗。该文设计了一种基于绝缘体上硅(SOI)结构的铁电负电容场效应晶体管,利用TCAD Sentaurus仿真工具对负电容晶体管进行仿真研究,得到了亚阈值摆幅为30.931 mV/dec的负电容场效应晶体管的器件结构和参数。最后仿真研究了铁电层厚度、等效栅氧化层厚度对负电容场效应晶体管亚阈值特性的影响。     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

SOI结构P型SiGe沟道混合模式晶体管器件模型研究

在带有应变SiGe沟道的SOIMOSFET结构中 ,把栅和衬底相连构成了新型的混合模式晶体管 (SiGeSOIBMHMT) .在SIVACO软件的器件数值模拟基础上 ,对这种结构的P型沟道管工作过程作了分析 ,并建立了数学模型 .提出在低电压 (小于 0 7V)下 ,衬底电极的作用可近似等效成栅 ,然后依据电荷增量 (非平衡过剩载流子 )的方法 ,推导出该结构的I V特性方程 .该方程的计算结果与器件模拟结果相一致.     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.     

Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region

This paper reports the shallow trench isolation (STI)-induced mechanical stress-related Kink effect behaviour of the 40 nm PD SOI NMOS device. As verified by the experimentally measured data and the 2D simulation results, the Kink effect behaviour in the saturation region occurs at a higher V_D for the 40 nm PD device with a smaller S/D length (SA) of 0.17 μm as compared to the one with the SA of 1.7 μm due to the higher body-source bandgap narrowing (BGN) effect on the parasitic bipolar device (BJT) from the higher STI-induced mechanical stress, offset by the impact ionization (II) enhanced by the BGN in the high electric field region near the drain.     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

SOI thermal impedance extraction methodology and its significancefor circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R_th) and thermal capacitance (C_th) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current