LS MPP编程语言研究

为了方便开发运行于LS MPP系统的应用程序,文章研究了LS MPP编程语言.首先,分析了现有LS MPP计算机的体系结构,以及作为其未来发展方向的图像处理器的概念模型.然后,介绍了对应该概念模型的中间语言和中间表示.最后,详细分析了该概念模型对应的高级语言扩展部分.分析表明,高级语言对概念模型描述的并行计算机性能的提高非常有益,使程序员的编程更加方便,并且降低了编译器的复杂性.     

LS系列嵌入式计算机汇编程序的一体化研究

文章通过LS－RISC、LS－MPP和LS－DSP嵌入式计算机指令系统的详细比较,对这三个系统汇编程序一体化的可行性进行了研究,提出了实现其汇编程序一体化的方案。     

基于Zigbee技术的智能家居系统的研究

新型短距离无线通信技术ZigBee 具有超低功率、低速率等优点, 很适合家庭网络的组建.本文以ZigBee 为基础,搭建嵌入式ARM处理器及嵌入式Linux相结合的应用环境,研究了智能家居系统,重点阐述了该系统的结构和技术上的可行性.     

LS MPP数据并行C语言编译器实现的研究

大规模并行处理技术是并行计算研究的一个热点问题,文章针对LS MPP嵌入式大规模并行处理机提出了一个数据并行C语言编译系统的实现方案,并对其中的代码分离、数据分布、节点程序生成等关键技术的实现进行了详细的阐述。     

LS MPP嵌入式计算机的系统软件设计

LS MPP是西安微电子技术研究所自行研制出的面向航空嵌入式应用的大规模并行图象处理机。其宿主机为自行研制的32位浮点RISC芯片，图象协处理系统为自行研制的MPP协处理器。文章论述了LS MPP计算机的系统软件设计，包括汇编程序、监控程序和C编译程序。     

应用于视频处理的可重构流处理器的设计与实现

设计了一款新的应用于多媒体处理领域的可重构多媒体流处理器.该可重构多媒体流处理器采用并行处理机制,在经过算法映射后,可以充分利用多媒体算法的高并行度,同时实时处理不同的多媒体算法.该架构在Xilinx的Virtex4芯片上通过验证,并与ARM9处理器共同构成嵌入式多媒体处理平台,验证处理H.264和AVS的解码过程.     

流体系结构密码处理器存储系统的研究与设计

以信息安全设备的密码应用需求为基础,融合流体系结构处理器基本架构,设计出流体系结构密码处理器.文章主要研究和设计影响该处理器性能的瓶颈--流存储系统.此系统针对专用密码处理器的存储特点,并采用可配置化设计,满足密码应用对处理器存储系统灵活高效的要求.同时,该设计将层次化-分布-分体式存储、多数据通道流水并行化访存、流访存调度策略相结合,优化存储系统的访存效率,以提高该处理器的整体性能.研究结果表明,相比于典型密码处理器的存储设计,该设计的访存效率最高可提升约6倍.     

一种基于ARM处理器的异常处理设计与实现

嵌入式系统要求对异常及中断处理器能快速响应。文中分析了ARM体系结构下异常处理特点,提出一种基于ARM处理器的高效异常处理解决方案,以LPC3250硬件平台为基础,对该方案进行了设计与实现。测试结果表明,该方案的异常处理更为高效。     

多重处理的设计选择:多处理器或多线程技术

现今,影响嵌入式市场的一个重要因素是,开发应用软件同样需要了解使用多重处理技术的通用处理器架构,这样才能使处理器实现更高的性能和更低的功耗。虽然多处理器和多线程技术都对嵌入式开发者提出了多重处理的复杂性问题,但对于不同的软件来说,他们在成本与复杂性方面有所不同。     

面向嵌入式应用的流处理调度技术研究

现有的嵌入式计算机无法满足新型武器系统更高的数据处理效能,迫切需要上层软件设计提升计算机的信息处理速率。文中基于流处理模式,提出一种面向嵌入式应用的流处理调度技术。该技术从计算资源优化分配管理、调度协同技术层面进行了详细分析,为全面提高嵌入式计算机的数据处理效能提供了上层算法支持。     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V     

基于S3C6410和WinCE6.0的嵌入式立体摄像系统

针对目前立体对图像同步采集问题,提出一种基于S3C6410处理器和WinCE6.0系统的实时同步采集方案.首先,完成立体摄像模块硬件设计;其次,开发相应的OV3640摄像头驱动程序并定制WinCE6.0操作系统;最后,开发基于DirectShow技术的立体摄像系统应用程序.应用程序利用摄像数据流反馈实现左右格式立体对图像的同步采集,关联左右两路摄像数据流,基于视差约束实现双摄像采集帧同步.系统利用ARM 11处理器的数据处理能力和WinCE系统的可裁剪,提高了嵌入式立体摄像系统的可靠性与便携性.     

基于S3C2440的Windows CE设备驱动的研究与实践

随着信息化、智能化、网络化的发展,嵌入式技术已经成为通信和消费类产品的共同发展方向。简要介绍嵌入式操作系统Windows CE,同时对Windows CE下两种基本的驱动开发模型本机设备驱动程序和流接口驱动程序进行重点说明。在了解两种模型的基础上,以基于S3C2440处理器的UART0驱动程序开发为例,详细介绍嵌入式操作系统Win-dows CE下流接口设备驱动开发的具体过程。     

结构化风格在逻辑模拟中的应用

本文论述了结构化设计思想在逻辑模拟中的应用，并用结构化设计思想对模拟对象进行层次划分，并用实际模拟过程作进一步论证。在本文的结尾做了理论性的总结。     

一个2D-Mesh上的完全自适应路由器设计

路由器在大规模并行处理机系统(MPP)中,对互连网络通信性能和系统性能发挥起着关键作用.本文根据所提出的完全自适应路由思想——基于通道方向的完全自适应路由,设计了一个2D-Mesh上完全自适应路由算法.进一步,采用了一种新的高速网络互连技术——源同步技术,最终设计、实现了一个高效、简洁的完全自适应路由器,并在Xilinx XACT的CAD工具上进行了模拟验证.     

A VLIW processor with reconfigurable instruction set for embedded applications

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-/spl mu/m CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3/spl times/ to 13.5/spl times/ and energy consumption reduced up to 92%.     

Power analysis and minimization techniques for embedded DSPsoftware

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged     

Streaming processors for next-generation mobile imaging applications

Next-generation mobile devices will continue to demand high processing power for imaging applications. The expected performance is in the class of supercomputers, but delivered with limited energy and memory bandwidth for embedded systems. This article advocates a streaming computation model that leverages the deterministic access patterns in imaging applications to deliver the necessary processing throughput. A reconfigurable datapath connects a set of functional units, forming a computation pipeline to offer energy efficiency. The architecture and implementation of a stream processor are presented along with the memory subsystem to support stream data transfers. The results show speedup ranging from a factor of 2 to 28 for imaging applications, offering favorable comparison against scalar processors.