Novel Single-Wafer Single-Chamber Dry and Wet Hybrid System for Stripping and In Situ Cleaning of High-Dose Ion-Implanted Photoresists

There is increasing demand for moving from batch immersion tools to single-wafer spin tools for silicon wafer cleaning, etching, and photoresist/residue removal in advanced semiconductor manufacturing. However, high-dodse ion-implanted photoresist removal using a conventional single-wafer spin tool is very difficult. We have developed a novel single-wafer single-chamber dry and wet hybrid system in combination with dry ashing and moderate-temperature wet-cleaning treatments by implementing an atmospheric-pressure plasma unit into a conventional single-wafer spin cleaning tool. This compact single-wafer single-chamber system can completely remove the hardened photoresist due to high-dose ion-implantation by an atmospheric-pressure plasma ashing process followed by an in situ wet chemical process in the same single chamber within 2 min. This single-wafer single-chamber dry/wet hybrid system offers less than 1/3 smaller footprint, less than 1/4 shorter cycle time (for 50 wafer processing), and potentially better process control and less contamination risk, as well as lower equipment cost, compared to the conventional combination of two separate dry- and wet-processing systems.      

Manufacturing benefits of disilane as a precursor for polycrystalline silicon films for the advanced CMOS gate electrode

The polycrystalline silicon deposited by single-wafer rapid thermal chemical vapor deposition with both silane (SiH/sub 4/) and disilane (Si/sub 2/H/sub 6/) precursors have been characterized for across wafer uniformity, thickness repeatability, and basic material properties such as grain structure and surface topography. The results show that the disilane process greatly improves the manufacturability of the single-wafer polycrystalline silicon process. Specifically, a /spl sim/50% improvement in the thickness uniformity, /spl sim/25% improvement in surface roughness, and a significantly less sensitivity of the process to hardware have been achieved with similar particle performance. The grain structure of as-deposited and postimplant and anneal films have been compared by X-ray diffraction and transmission electron microscope. NMOS and PMOS capacitors have been fabricated with polycrystalline silicon using silane and disilane precursors. The grain structure and electrical parameters, such as gate leakage currents and gate capacitance, show no significant difference between these two precursors.     

Single-wafer/mini-batch approach for fast cycle time in advanced 300-mm fab

Advanced 300-mm application specific integrated circuit/system-on-chip (ASIC/SOC) fabs with multiproduct and multiprocess models will require both a high level of flexibility and efficiency to achieve cost effective manufacturing cycle times. One of the main detractors for cycle time and fab flexibility is a batching requirement on certain types of processing that makes lots waiting for the batch to be completed and generates wip bubbles downstream. This paper reviews the front-end steps within a semiconductor manufacturing flow where batching requirements may be replaced by single-wafer or mini-batch alternatives for improved cycle time. Encouraging process results for front-end applications for potential single-wafer replacements are presented. It is demonstrated that single-wafer oxidation, LPCVD and cleaning offer a large potential cycle time gain but currently have different levels of maturity as potential batch technology replacements. In addition to the process feasibility, a DOE based on dynamic simulation is conducted enabling the quantification of potential gains in cycle time obtained by switching to single-wafer or mini-batch strategy instead of batch strategy, preferring integrated metrology and reducing mini-lots size. It shows that, in comparison to the baseline model (100%), the manufacturing cycle time may decrease down to 65% for mini-lots and to 78% for standard production lots.     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

Cost and cycle time performance of fabs based on integratedsingle-wafer processing

Visions of future wafer fabs include the use of integrated single-wafer processors to achieve fast cycle times and contain rising production costs. A survey of IC manufacturers, equipment vendors, and IC manufacturing literature was used to generate hypothetical conventional and alternative fabs to evaluate the effect of integrated single-wafer processing on cycle time and cost performance. The distinguishing features of the alternative fab are: (1) all thermal processes performed on single-wafer processors; (2) back-end net cleans performed on single-wafer processors; (3) integration of single-wafer processors into clusters or cells wherever practical, and (4) extensive use of in situ process monitors to replace in-line process monitors. Modeling and simulation of the resulting fabs suggest that integrated single-wafer processing can reduce the cycle time of conventional fabs by about 50% without having a significant effect on wafer production test. Tool integration and single-wafer processing must be used together to achieve these performance improvements. Although traditional lot sizes appeared to be appropriate for both fabs, improvements in cluster tool reliability and process step similarity could change optimal integrated tool configurations and reduce optimal lot sizes in the future     

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-/spl mu/m logic process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.     

Manufacturability of rapid-thermal oxidation of silicon: oxidethickness, oxide thickness variation, and system dependency

The dependence of oxide thickness, and oxide thickness variation within a wafer and wafer-to-wafer on process variables was studied in rapid-thermal processing systems that differed in chamber configuration and construction, incoherent light source, and pyrometers used for temperature measurement. Mechanisms for oxide growth and oxide thickness variation in rapid-thermal oxidation are discussed. Thermally induced stress, lamp configuration, and convective cooling affected the oxide thickness variation within a wafer. Wafer-to-wafer oxide thickness variation depended on the material of chamber construction, quartz or metal, and was related to residual heating for longer oxidations. For the same processing conditions, the oxide thickness was different for different systems, due to temperature error and a photonic component to rapid-thermal oxidation. Analysis of empirical oxide thickness models revealed a silicon orientation effect and a mechanism related to oxidant transport that was common to rapid-thermal oxidation in different systems     

适用于小型生产线运行的单晶圆清洗技术的实现(英文)

利用臭氧消毒水和淡氟氢酸清洗技术,使设备生产厂家的单晶圆旋转清洗工艺适应向小型生产线转入的应用,从而使生产周期的缩短成为可能。     

Applications of single-wafer rapid-thermal processing to the manufacture of advanced flash memory

The application of single-wafer processing in semiconductor manufacturing has long been touted as the most effective way in reducing cycle time in a production environment as well as shortening the learning cycle for process development. However, one of the bottle neck areas is in the diffusion module in which conventional furnace processes are difficult to replace due to their superior film quality and high throughput. Recently, significant progress has been made in the areas of rapid thermal oxidation (RTO) and low-pressure chemical vapor deposition (LPCVD) such that high quality films of oxide, nitride, and polysilicon were achieved with great improvement in manufacturing cycle time. In this paper, nonvolatile memory devices such as flash EPROM will be used as examples to illustrate the effective applications of RTO and single-wafer LPCVD processes.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Single-wafer polysilicon engineering for the improvement of over erase in a 0.18-/spl mu/m floating-gate flash memory

A new polysilicon grain engineering technology for the improvement of over erase in 0.18-/spl mu/m floating-gate flash memory has been developed with the use of single-wafer polysilicon processing, which makes it practical to use hydrogen as a process variable. The addition of hydrogen in polysilicon deposition significantly alters the reaction kinetics and produces polysilicon thin film of smooth surface, fine and uniformly distributed grains. Such a micrograin polysilicon possesses show excellent high-temperature stability. The benefits of the micrograin polysilicon are to be demonstrated through its improvement in over erase of a 0.18-/spl mu/m floating-gate flash memory.     

Formation of MOS Gates by rapid thermal/microwave remote-plasma multiprocessing

A novel cold-wall single-wafer lamp-heated rapid thermal/ microwave remote-plasma multiprocessing (RTMRPM) reactor has been developed for multilayer in-situ growth and deposition of dielectrics, silicon, and metals. This equipment is the result of an attempt to enhance semiconductor processing equipment versatility, to improve process reproducibility and uniformity, to increase growth and deposition rates at reduced processing temperatures, and to achieve in-situ processing. For high-performance MOS VLSI applications, a variety of selective and nonselective tungsten deposition processes were investigated in this work. The tungsten-gate MOS devices fabricated using the remote-plasma multiprocessing techniques exhibited negligible plasma damage and near-ideal electrical characteristics. The flexibility of the reactor allows independent optimization of each process step yet permits multiprocessing.     

Single-wafer process technology: enabling rapid SiGe BiCMOS development

This paper explores the application of single-wafer processing (SWP) tools to rapidly create high-value added, innovative processes technologies, using the example of SiGe BiCMOS process technology development to highlight the unique advantages that SWP provides to rapidly develop a cost-effective and innovative platform. This paper also reviews the unique requirements necessary for SiGe BiCMOS technology development. SWP equipment is shown to be ideally suited to meeting both the technical and schedule requirements for rapidly and efficiently executing a technology development plan. In addition, the flexibility of single-wafer tooling is well suited to a lower volume technology without compromising the ability to modularly scale the SiGe unit process to meet higher volume production requirements.     

Effect of UV/VUV enhanced RTP on process variation and device performance of metal gate/high-/spl kappa/ gate stacks for the sub-90-nm CMOS regime

We show that UV/VUV-enhanced rapid thermal processing (RTP) in combination with single-wafer processing using a single tool for the fabrication of metal gate/high-/spl kappa/ dielectric gate stacks not only improves overall device performance, but also leads to a significant reduction in process variation at the front end of the CMOS process flow for the sub-90-nm technology node. The gate stacks were fabricated under various UV/VUV conditions. Gate stacks processed under UV/VUV radiation during all processing steps displayed low leakage currents of the order of 10/sup -11/ A/cm/sup 2/. It is shown that the Al-Al/sub 2/O/sub 3/-Si gate stacks processed under UV/VUV conditions also display the lowest variations both in mean leakage current and mean capacitance, as compared to devices where UV/VUV was not used for all the processing steps. Therefore, it can be see that reliance on successive corrective iterations common to automatic process control or standard design simulation can be reduced significantly. As a result, UV/VUV-enhanced RTP has the potential to reduce the effect of process variations on overall device performance, thereby making the overall process more cost effective and time efficient and therefore improving yield and device reliability.     

Manufacturability issues in rapid thermal chemical vapor deposition

Rapid thermal processing (RTP) has been considered from a manufacturing point of view as a potential technology for depositing thin films by low-pressure chemical vapor deposition (LPCVD) in a single-wafer manufacturing environment. The results of this study suggest that new chemical processes must be developed to satisfy the throughput requirements of single-wafer manufacturing and the demands of cold-wall reactor design. Issues such as temperature measurement and uniformity are reviewed and reconsidered in the context of LPCVD. New tool requirements for reduced pressure operation are discussed. New advances in tool design are needed (especially in temperature measurement) before rapid thermal chemical vapor deposition (RTCVD) can be considered as a routine manufacturable process     

Single-wafer integrated semiconductor device processing

The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described     

A review: Thermal processing in fast ramp furnaces

The capabilities and advantages of advanced batch furnaces in meeting semiconductor process requirements (up to a minimum of 100 nm technology node) are reviewed. Hot wall batch furnaces continue to provide accurate temperature control, low cost of ownership, and process advantages as compared to single-wafer tools. Recent advances by various furnace vendors have addressed the hot-walled furnace shortcomings of thermal response, process times, and automation overload, resulting in improved manufacturing economics. The inherent benefits such as large load size, isothermal processing, uniform film growth, high reliability, and low capital cost have ensured a substantial cost of ownership advantage over single-wafer processes. Accurate temperature modulation at high temperatures during both heating and cooling cycles has allowed synthesis of ultra thin gate oxides for devices below sub-200 nm design rule.     

The effect of ion-implantation damage on dopant diffusion in silicon during shallow-junction formation

Low-thermal-budget annealing of ion-implanted BF ₂ ⁺ , P, and As in Si was studied for shallow-junction formation. Implant doses were sufficient to amorphize the silicon surface region. Low-temperature furnace annealing and rapid-thermal annealing of ionimplanted boron, phosphorus and arsenic in silicon exhibit a transient enhanced diffusion regime resulting injunction depths considerably deeper than expected. The origin of this transient enhanced diffusion is the annealing of ion-implantation damage in the silicon substrate. We have found that point-defect generation during the annealing of either shallow end-of-range damage or small clusters of point defects dominates the transient enhanced diffusion process depending upon the annealing temperature and time. The net effect of damage annealing is to reduce the activation energy for dopant diffusion by an amount equal to the activation energy of the supersaturation of point defects in silicon. Models which can describe the transient enhancement characteristics in dopant diffusion during both furnace and rapid-thermal annealing of these implants are discussed.     

Online Scheduling of Integrated Single-Wafer Processing Tools With Temporal Constraints

This paper addresses the issues of online scheduling for integrated single-wafer processing tools with temporal constraints. The integrated single-wafer processing tool is an integrated processing system consisting of single-wafer processing modules and transfer modules. Certain chemical processes require that the wafer flow satisfies temporal constraints, especially, postprocessing residency constraints. This paper proposes an online scheduling method that guarantees both logical and temporal correctness for the integrated single-wafer processing tools. First, mathematical formulation of the scheduling problem using temporal constraint sets is presented. Then, an online, noncyclic scheduling algorithm with polynomial complexity is developed. The proposed scheduling algorithm consists of two subalgorithms: FEASIBLE_SCHED_SPACE and OPTIMAL_SCHED. The former computes the feasible solution space in the continuous time domain, and the latter computes the optimal solution that minimizes the completion time of the last operation of a newly inserted wafer.     

A wafer-handling interface under processing ambient conditions fora single-wafer cluster tool

The pretreatment process used in semiconductor manufacturing can include over one-hundred processes, and about 90% of the wafer transfers are done between processors or process chambers that have different ambient conditions from each other; that is, between the atmosphere and a vacuum ambient or between a low and a high vacuum ambient. The throughput and yield from a semiconductor manufacturing line can be greatly improved by reducing the pumping and setting time of each process chamber ambient that is needed when transferring a wafer. We previously proposed a wafer-handling interface that operates under processing ambient conditions (the WHIPAC), with which the processing ambient conditions in the process chamber need not be changed for every wafer exchange and processing ambient fluctuations can be made smaller. We have developed a WHIPAC that allows the wafer in a process chamber under processing ambient conditions to be exchanged with a small mobile buffer chamber located in the transfer chamber at the center of a cluster tool used for single-wafer processing. This paper describes the principle of the WHIPAC for a single-wafer cluster tool and discusses the experimental results obtained from tests of a prototype system