嵌入式粗颗粒度可重构处理器的软硬件协同设计流程

 面向多媒体应用的可重构处理器架构由主处理器和动态配置的可重构阵列(Reconfigurable Cell Array,RCA)组成.协同设计流程以循环流水线和流水线配置技术为基础,采用启发式算法对应用中较大的关键循环进行了软硬件划分,使用表格调度算法实现了任务在RCA上的映射.经过FPGA验证,H.264基准中的核心算法平均执行速度相比于PipeRench,MorphoSys,以及TI DSP TMS320C64X提高了3.34倍.     

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundamental problem is the placement of the modules on the reconfigurable functional unit (RFU). In reconfigurable systems, we are interested both in online placement, where arrival time of tasks is determined at runtime and is not known a priori, and offline in which the schedule is known at compile time. In the case of offline placement, we are willing to spend more time during compile time to find a compact floorplan for the RFU modules and utilize the RFU area more efficiently. In this paper we present offline placement algorithms based on simulated annealing and greedy methods and show the superiority of their placements over the ones generated by an online algorithm.     

UPRFloor:一种动态可重构FPGA建模方法与布局策略

针对现场可编程门阵列（Field Programmable Gate Array,FPGA）布局过程中片上可重构资源利用率低与通信开销过高问题,本文提出了一种支持多描述模型的布局策略Union Partial Reconfiguration Floorplans（UPRFloor）.首先,该策略根据逻辑功能客观形状,定义了矩形、非矩形多描述模型,然后利用混合整数线性规划方法,从可重构资源利用率、逻辑功能间通信开销与逻辑功能内部通信开销三个方面进行多目标优化,实现了三者之间相互影响与共同作用下的最优布局方案.该策略已在FPGA芯片上进行了仿真布局,结果表明：与基于矩形模型的布局方法相比,UPRFloor布局策略在资源利用率方面最高有25.59%的提升.在Microelectronics Center of North Carolina（MCNC）标准测试集上的对比实验表明：在耗时几乎相同的情况下,UPRFloor较其它算法的布线长度最多减少了22.49%;在Software Defined Radio（SDR）测试数据中,UPRFloor在节约29.41%可重构资源的同时,布线长度节省了13.41%,从而有效降低了资源浪费与通信开销.     

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications

A run-time reconfigurable multiply-accumulate (MAC) architecture is introduced. It can be easily reconfigured to trade bitwidth for array size (thus maximizing the utilization of available hardware); process signed-magnitude, unsigned or 2's complement data; make use of part of its structure or adapt its structure based on the specified throughput requirements and the anticipated computational load. The proposed architecture consists of a reconfigurable multiplier, a reconfigurable adder, an accumulation unit, and two units for data representation conversion and incoming and outgoing data stream transfer. Reconfiguration can be done dynamically by using only a few control bits and the main component modules can operate independently from each other. Therefore, they can be enabled or disabled according to the required function each time. Comparison results in terms of performance, area and power consumption prove the superiority of the proposed reconfigurable module over existing realizations in a quantitative and qualitative manner.     

基于拓扑感知的可重构服务承载网动态重构算法

可重构信息通信基础网络通过构建服务承载网的方式为业务提供自适应的承载服务。针对高效利用有限底层资源的问题,提出一种基于资源关键度进行动态映射的服务承载网构建算法。算法将通过节点或链路的最短路径数作为资源关键度的衡量指标,区别对待底层资源;并实时动态感知关键资源的使用状况,依据不同业务需求对服务承载网进行自适应调整。仿真结果表明,算法在构建成功率、收益花费比和资源均衡度等方面均具有良好性能。     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

一种考虑执行延迟最小化和资源约束的改进层划分算法

 本文提出了一种改进的层划分算法.该算法充分考虑了划分块的最小执行延迟和尽可能充分利用可重构资源,能够跟踪层划分算法节点分配过程并进行调整,消除了经典层划分算法不能动态更新就绪节点列表选取节点进行划分的缺陷.实验结果表明,与层划分算法相比,所提出的改进层划分算法在模块数、执行延迟和跨模块间的I/O边数等三个方面均获得了改进.与现有的簇划分、增强静态列表、多目标时域划分、簇层次敏感等四种划分算法相比,新算法能获得最少的执行延迟,并且随着可重构处理单元面积的增大,模块数的均值也是最小的.     

融合面积估算和多目标优化的硬件任务划分算法

针对可重构计算机系统配置次数(划分块数)的最小化问题,提出了一种融合面积估算和多目标优化的硬件任务划分算法。该算法每次划分均进行硬件资源面积的估算,并且通过充分考虑可重构资源的使用、一个数据流图所有划分块执行延迟总和、划分模块间边数等因素构造了新的探测函数prior_assigned(),该函数能够计算每个就绪节点的优先权值,新算法通过该值能动态调整就绪列表任务节点的调度次序。实验结果表明,与现有的层划分、簇划分、增强静态列表、多目标时域划分、簇层次敏感等5种划分算法相比,该算法能获得最少的模块数,并且随着可重构处理单元面积的增大,除层划分算法之外,其执行延迟的均值也是最小的。     

Hop count based optimization of Bluetooth scatternets

In the past five years Bluetooth scatternets were one of the most promising wireless networking technologies for ad hoc networking. In such networks, mobility together with the fact that wireless network nodes may change their communication peers in time, generate permanently changing traffic flows. Thus, forming an optimal scatternet for a given traffic pattern may be not enough, rather a scatternet that best supports traffic flows as they vary in time is required.In this paper we study the optimization of scatternets through the reduction of communication path lengths. After demonstrating analytically that there is a strong relationship between the communication path length on one hand and throughput and power consumption on the other hand, we propose a novel heuristic algorithm suite capable of dynamically adapting the network topology to the existing traffic connections between the scatternet nodes. The periodic adaptation of the scatternet topology to the traffic connections enables the routing algorithms to identify shorter paths between communicating network nodes, thus allowing for more efficient communications. We evaluate our approach through simulations, in the presence of dynamic traffic flows and mobility.     

Synthesis and Time Partitioning for Reconfigurable Systems

This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.     

基于SytemC动态可重构系统硬件任务管理模型

采用基于框架的建模仿真方法,对动态可重构系统进行设计空间搜索,需要建立仿真模型评估任务的管理策略.为此,文中利用SystemC搭建了一种动态可重构系统的硬件任务管理模型,该模型可根据不同的管理策略和重构资源进行调整.仿真实验结果表明,通过模型仿真获得硬件任务,在指定管理策略和资源约束下的实时调度布局信息,并针对具体应用...     

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-2²/2³/2⁴ FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.     

Hybrid Dual-Mode Frequency Synthesis for Cognitive Multi-radio Front-Ends

This paper investigates a novel approach to reconfigurable frequency synthesis for flexible radio transceivers in future cognitive multi-radios. The frequency range covered by the proposed multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards operating in the radio band ranging from 800 MHz to 6 GHz. A hybrid phase locked loop (PLL) based frequency synthesizer is proposed here and a novel switching protocol is presented and validated on an experimental evaluation board. The proposed architecture combines fractional and integer PLL modes of operation along with a switched loop filter topology. Compared to standard PLL techniques, the proposed configuration provides great flexibility options and moreover, it offers relatively low circuit complexity and low power consumption. The proposed architecture provides reconfigurability of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards.     

Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

On-chip bus design has a significant impact on the die area, power consumption, performance and design cycle of complex system-on-chips (SoCs). Especially, for high frequency systems having on-chip buses pipelined extensively to cope with long wire delay, a naive bus design may yield a significant area/power cost mostly due to bus pipeline cost. The topology, floorplan, and pipeline are the most important design factors that affect the cost and frequency of the on-chip bus. Since they are strongly correlated with each other, it is imperative to codesign all of the three. In this paper, we present an automated codesign method for cascaded crossbar bus design. We present CADBUS (CAscadeD crossbar BUS design tool), an automated tool for AXI-based cascaded crossbar bus architecture design. The primary objective of this study is to design a cascaded crossbar bus, including the topology/floorplan/bus pipelines, having minimum area/power cost while satisfying the given constraints of communication bandwidth/latency or frequency. Experimental results of the three industrial strength SoCs show that, compared to the existing approach, the proposed method gives as much as 11.6%–34.2% (9.9%–33.5%) savings in bus area (power consumption).      

基于可重构SoC电路的验证和应用

文章介绍了一款新型可重构SoC电路,较详细地描述了它的内部结构和特点,并制定应用方案,分别重构SPI和DDS模块,对该电路进行验证.应用方案中,利用SPI与VS1003连接,通过该SPI接口控制并发送歌曲数据给VS1003,VS1003对数据进行解码处理,最后驱动功放播放歌曲.利用DDS模块产生信号数据,经过D/A转换...     

一种适用于空间飞行器的可重构信息处理平台硬件设计

在我国空间通信技术取得巨大发展的今天,对空间飞行器电子设备功能可重构、可升级、运行代码可更换的需求越来越多。分析了空间辐射效应对高性能数字信号处理器（DSP）和SRAM型FPGA的影响,提出了一种适用于空间飞行器上的可重构信息处理平台的硬件设计方法,具有可重构、可在线升级运行代码的特点。该硬件架构计由高性能DSP和高可靠性的反熔丝FPGA为主要组成,提出了这种架构对抗空间单粒子效应的方法。该电路设计方法可以为空间飞行器通信设备的设计提供参考。     

全数字可配置信道分路技术的设计方法

提出一种全数字可配置信道分路技术的设计方法,是针对多相阵列FFT算法进行的一种串行结构设计,能够按照分路路数灵活配置多相滤波器组和FFT级数,可支持甚至达到上百路的分路路数。对全数字可配置信道分路的设计方法中涉及到的多相滤波器组和FFT两个主要模块的FPGA实现方法进行了详细阐述。基于该设计方法进行了4路、8路和16路信道分路应用的FPGA硬件设计,给出了硬件占用资源情况和误码测试结果,从而证明该设计方法的可实现性。     

一种粗粒度可重构体系结构多目标优化映射算法

针对多约束下的行流水粗粒度可重构体系结构的硬件任务划分映射问题,提出了一种多目标优化映射算法.该算法根据运算节点执行时延、依赖度等因素构造了累加概率权值函数,在满足可重构单元面积和互连等约束下,通过该函数值动态调整就绪节点的映射调度次序,当一块可重构单元阵列当前行映射完毕后,就自动换行,当一块阵列被填满,就切换到下一块,当一个数据流图映射完毕后,就自动计算划分块数等参数.实验结果表明,与层贪婪映射算法相比,文中算法平均执行总周期降低了8.4%(RCA_4×4)和5.3%(RCA_6×6),与分裂压缩内核映射算法相比,文中算法平均执行总周期降低了20.6%(RCA_4×4)和21.0%(RCA_6×6),从而验证了文中提出算法的有效性.     

REALISM:一种面向未来异构无线网络演进的架构

未来无线通信系统将是各种无线接入技术和标准的融合,包容各自独立的网络,形成通用的平台并以简便的协议和信令操作,来实现异构网络融合是我们提出REALISM(REconfigurable:Adaption Layer for Integrated SysteM)的初衷,它通过在协议栈添加适配层(REAL:REconfigurable Adaption Layer),为由WLAN和UMTS组成的无线异构网络提供了融合的平台.文章重点关注了REALISM架构中的主要功能模块;然后描述了无线资源管理方面功能的实现,并以切换管理,例进行详细阐述.     

一种应用于4G/5G频段的新型8×8频率可重构MIMO系统设计

文章提出一种可应用于4G/5G工作频段且应用分集技术解耦的8×8频率可重构MIMO系统。八天线阵列中包括4个可切换于2.6 GHz频段和3.5 GHz频段的频率可重构天线模块以及4个应用于3.5 GHz频段的5G模块。由于频率可重构技术的应用,该系统可满足网络传输速率等多种要求,进一步提高终端设备的空间利用率和系统应用的灵活性。文章给出了MIMO系统切换前后的S参数和包络相关系数等参数的计算结果,结果显示出多天线阵列的可应用性。