Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

A new model for the description of gate voltage and temperaturedependence of gate induced drain leakage (GIDL) in the low electricfield region [DRAMs]

Gate induced drain leakage (GIDL) is frequently described by band-to-band tunneling. This mechanism is insensitive to temperature and occurs only under strong electric fields. Under the condition of small electric fields, however, GIDL exhibits a strong dependence on temperature, which is due to trap-assisted generation of electron hole pairs. This generation mechanism is based on the Shockley-Read-Hall (SRH) equation involving field dependent emission probabilities due to Fowler-Nordheim (FN) and Poole-Frenkel effect. The proposed model of an acceptor-like interface trap is able to reproduce the experimental results. Temperature and voltage dependencies for a p-MOSFET are correctly calculated for one single fitting parameter, i.e., the interface trap density corresponding to N_t=1×10¹⁴ (1/eV m²)     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

Effects of plasma charging damage on the noise performance ofthin-oxide MOSFET's

The effects of plasma charging damage on the noise properties of MOSFET's which is a necessary consideration for high-performance analog applications were studied using 1/f noise, Random Telegraph Signal (RTS) noise and charge pumping techniques. Plasma ashing significantly increases the drain flicker noise, more with larger antenna sizes, mainly in the low-frequency and low-gate-bias regime. The observed RTS reveals that an oxide trap with a few milliseconds time constant was induced by the plasma processing. This oxide trap is located in the energy space which corresponds to the low gate bias of device. This trap may be reproduced by Fowler Nordheim stress as suggested by noise and charge pumping measurements, supporting the notion that plasma ashing damage is a result of electrical stress, not radiation, for example     

1/f noise in MOS devices, mobility or number fluctuations?

Recent experimental studies on 1/f noise in MOS transistors are reviewed. Arguments are given for the two schools of thought on the origin of 1/f noise. The consequences of models based on carrier-number ΔN or mobility fluctuations Δμ on the device geometry and on the bias dependence of the 1/f noise are discussed. Circuit-simulation-oriented equations for the 1/f noise are discussed. The effects of scaling down on the 1/f noise is studied in the ohmic region as well as in saturation. In the ohmic region the contribution of the series resistance often can be ignored. However, in saturation the noise of the gate-voltage-dependent series resistance on the drain side plays a role in lightly doped drain LDD mini-MOST's. Surface and bulk p-channel devices are compared and the differences between n-and p-MOST's often observed is discussed. The relation between degradation effects by hot carriers or by γ-irradiation on the one hand and the 1/f noise on the other is considered in terms of a ΔN or Δμ. Experimental results suggest that 1/f noise in n-MOST's is dominated by ΔN while in p-MOST's the noise is due to Δμ     

A physical and scalable I-V model in BSIM3v3 for analog/digitalcircuit simulation

A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I_ds, conductances and their derivatives throughout all V_gs, V_ds, and T_bs, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on     

An analysis of space-charge-region recombination in HBT's

The importance of including recombination in the base side of the emitter-base space-charge-region (SCR) in the computation of the current gain in AlGaAs/GaAs HBT's is investigated. Recombination due to Shockley-Read-Hall, Auger and radiative processes is considered. The interaction of the base-side SCR recombination currents with the neutral-base current and the collector current, which occurs via their dependence on the quasi-Fermi level splitting (ΔE_fn) at the base-emitter junction, is not found to be a significant factor in the computation of ΔE_fn. However, it is confirmed that the quasi-Fermi level splitting, as calculated from a balancing of the thermionic/tunnel current with the neutral base and collector currents, must subsequently be included in the computation of the base-side SCR currents if the current gain is not to be severely underestimated. A discussion of why the ideality factor is ≈1 for the base-side SCR currents is given. Finally, simple analytical expressions for ΔE _fn and the SCR recombination currents are presented and should prove useful for HBT device- and circuit-simulation purposes     

Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolartransistors

In this work a comprehensive investigation of low-frequency noise in ultrahigh vacuum/chemical vapor deposition (UHV/CVD) Si and SiGe bipolar transistors is presented. The magnitude of the noise of SiGe transistors is found to be comparable to the Si devices for the identical profile, geometry, and bias. A comparison with different technologies demonstrates that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs heterojunction bipolar transistors (HBT's) and conventional Si bipolar junction transistors (BJT's). Results from different bias configurations show that the 1/f base noise source is dominant in these devices. The combination of a 1/Area dependence on geometry and near quadratic dependence on base current indicates that the 1/f noise sources are homogeneously distributed over the entire emitter area and are probably located at the polysilicon-Si interface. Generation/recombination (Gm) noise and random telegraph signal (RTS) noise was observed in selected Si and SiGe devices. The bias dependence and temperature measurements suggest that these G/R centers are located in the base-emitter space charge region. The activation energies of the G/R traps participating in these noise processes were found to be within 250 meV of the conduction and valence band edges     

Effect of forward and reverse substrate biasing on low-frequencynoise in silicon PMOSFETs

Forward body biasing improves the low-frequency noise performance of p-channel metal-oxide semiconductor (PMOS) transistors by about 8 dB/V. Therefore, for analog design, forward body biasing may be preferred if noise is a concern. This is in agreement with the improvement of other MOSFET parameters such as the decrease of the threshold voltage (V_T) or the increase of unity current-gain frequency (f_T) on forward substrate- (or body)-source biasing (V_BS). Also, forward V_BS is very attractive for low voltage supply (V_DD<0.6 V) and low-power, low-noise circuits. A detailed analysis of the dependence of the noise level on VBS and on the gate-source (V_GS) biasing showed that the dependence on V_BS seems to be smaller in weak inversion, and it increases in strong inversion. The dependence on V_GS has a turning point at V_GS≈0.8 V, independent of body bias, which it seems is due to the activation of oxide traps, as the noise waveform showed a random telegraph signal (RTS) component at V_GS >0.8 V. Generally, it is confirmed that the spectral density S _I of the total low-frequency noise of the drain current I_D is proportional to the square of I_D, i.e., S _I∝I_D², but it cannot be clearly ascribed to either number fluctuation or mobility fluctuation models. In addition, both models cannot accurately describe the dependence of the noise level on the body bias     

Statistical BSIM model for MOSFET 1/f noise

A statistical model for MOSFET 1/f noise implemented as an extension to BSIM and integrated into a process design kit is presented. Excellent model to hardware correlation is shown on measured noise statistics from over 200 devices. The statistical model enables circuit designers to run Monte Carlo and corner noise simulations, and captures the device area and bias dependence of noise variance.     

Critical discussion on unified 1/f noise models for MOSFETs

Recently, unified noise models, like BSIM3, have been proposed in literature to describe the 1/f noise of n- and p-type MOSFETs in all operating regimes. These models combine carrier number fluctuations and correlated mobility fluctuations. The latter are induced by the Coulomb scattering of free carriers at trapped interface charge. The unified 1/f noise models assume implicitly that the mobility, limited by Coulomb scattering, does not depend on the inversion carrier density. However, this assumption is not correct in view of theoretical calculations and recent experimental results. In this paper, we show that the correlated mobility fluctuations are negligible, if the correct dependence on inversion carrier density is taken into account for the Coulomb scattering limited mobility. Consequently, the unified 1/f noise models cannot predict the 1/f noise observed experimentally in p-type MOSFETs, except if nonphysical fitting parameters are used. This paper serves as a critical discussion on the unified 1/f noise models for MOSFETs. Here it is not our intention to propose a new 1/f noise model     

The gate bias and geometry dependence of random telegraph signalamplitudes [MOSFET]

A new random telegraph signal (RTS) amplitude model based upon band bending fluctuations has been developed, in contrast to other studies of RTS noise amplitudes, which are derived from RTS fitting parameters, it is demonstrated in this work that noise amplitudes may be predicted from band bending calculations and device DC characteristics. This new model suggests that the decrease in band bending associated with slow-state trapping results in mobility degradation for low gate biases (Coulombic-scattering-limited) and an enhancement in mobility due to vertical field reductions at high gate biases (surface roughness/phonon scattering limited). The band bending formulation shows good correlation with experimental data and accurately predicts the observed dependence upon effective channel length and width     

Numerical confirmation of inelastic trap-assisted tunneling (ITAT)as SILC mechanism

This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density N_t, and the trap energy level E_t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N _t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10^-13 s and E_t of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well     

Empirical modeling of LF gate noise in GaAs DCFET in impactionization regime

The evolution of the 1/f gate noise in GaAs DCFET has been analyzed in the impact ionization regime. As the drain bias Vd is raised, a steep increase of the 1/f gate current noise is observed in correlation with the triggering of the impact ionization mechanism. A novel and empirical model of the 1/f low frequency gate current noise S _ig measured in the impact ionization regime is proposed. The following relation fits it with an exponential law: S_ig=E exp (-F/Vd) (1/f), which is similar to the well-known dependence of the impact ionization rate α on the drain bias     

基于迁移率波动的MOSFET线性区域1／f噪声模型

统一的1/f噪声模型,例如BSIM3模型,已经在噪声预测与分析中有着广泛的应用,在多数情况下有很好的效果.然而文献[1]中基于物理机理分析的研究表明,统一的1/f噪声模型对处于线性区p-MOSFET不能进行正确的描述:当偏置电压V_gs增加时,该模型低估了噪声功率的增加.据此,本文提出了一种基于物理机理的迁移率波动(MF)1/f噪声模型,并给出了新MF模型与统一的1/f噪声模型在线性区的仿真结果.从仿真结果可以看出,新噪声模型更接近于测试的结果.     

A model for 1/f noise in diffusion current based on surfacerecombination velocity fluctuations and insulator trapping

In this paper we present a new model for low frequency 1/f noise in semiconductor diodes. The model describes noise in diffusion current due to fluctuations in surface recombination velocity. The fluctuations in surface recombination velocity are in turn caused by insulator trapping. We examine the model's predictions for 1/f noise and its dependence on device geometry, temperature, surface potential, majority carrier concentration, and trap energy. Example calculations are performed for narrow band gap HgCdTe (E_G=0.125 eV at 77 K), for which this mechanism should be relevant     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

MOSFET中大幅度随机电报信号噪声的动力学特性

对 MOSFET器件的随机电报信号噪声 ( RTS)的特征进行了研究。室温下在极细沟道样品中观测到了大幅度 (大于 60 % )的 RTS,通过测量 RTS的俘获时间和发射时间与栅压和温度的依赖关系 ,获得了氧化层陷阱的位置与能级 ,证实了氧化层陷阱的热激活模型在细沟道 n MOSFET中仍然成立。同时发现当器件工作在弱反型区时 ,RTS幅度基本与栅压无关。对 RTS的动力学机制的分析及数值模拟表明 ,当沟道宽度减小至 4 0 nm以下时 ,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对 RTS的幅度的影响起主导作用。     

Correlation between 1/f noise and hFElong-term instability in silicon bipolar devices

Accelerated life tests with high-temperature storage and electric aging for n⁺-p-n silicon planar transistors were carried out. Current gain h_FE increases monotonously with time during the tests, and the h_FE drift is correlated with initial measured 1/f noise in the transistors, i.e. the drift amount significantly increases with the increase of noise level. The correlation coefficient of relative drift Δh_FE /h_FE and 1/f noise spectral density S_iB(f) is far larger than that of Δ h_FE/h_FE and initial DC parameters of the transistors. A quantitative theory model for the h _FE drift has been developed and explains the h _FE drift behavior in the tests, which suggests that the h _FE drift and 1/f noise can be attributed to the same physical origin, and both are caused by the modulation of the oxide traps near the Si-SiO₂ interface to Si surface recombination. 1/f noise measurement, therefore, may be used as a fast and nondestructive means to predict the long-term instability in bipolar transistors     

Random telegraph noise and leakage current in smart power technology DMOS devices

Random telegraph signal (RTS) noise, analyzed in time and frequency domains, and leakage current are studied in smart power technology double-diffused metal oxide semiconductor (DMOS) field effect transistors. The RTS noise is strongly correlated with the presence of an excess leakage current in the device. The observed drain current (gate bias) dependencies of relative (absolute) RTS amplitude and gate voltage dependence of RTS mean pulse widths suggest that the RTS noise sources are located under the gate and in the drain-body region. A model, where the multicell DMOS structure is considered as parallel connection of submicron MOSFETs, is proposed to account for the results.