HDP-CVD STI oxide process with in situ post deposition laterally enhanced sputter etchback for the reduction of pattern-dependent film topography in deep submicron technologies

This paper introduces a postdeposition pattern-dependent topography-reduction enhancement to the high-density plasma chemical-vapor deposition (HDP-CVD)oxide profile for shallow trench isolation in deep submicron technologies. The enhancement is labeled "laterally enhanced sputter etchback" (L-SEB) and is carried out in situ in the HDP-CVD reactor after film deposition. The L-SEB is set up using O/sub 2/ and Ar at high O/sub 2/ flow. A design of experiment was run to search for optimum gas flow conditions. The optimized process is shown to yield significant lateral "pull-in" of the sizeable HDP oxide cones over large thin-oxide features and flattening of smaller cones over dense small features, without appreciable impact on field oxide (FOX) thickness or corner integrity. This contributes a significant improvement to an STI module that incorporates downstream planarization processes of reverse-tone etch (RTE) and chemical mechanical polishing (CMP). It also allows a start with a thinner film thickness and usage of a smaller lithography compensation factor for the reverse-tone mask, thus facilitating a smaller minimum feature for RTE exposure. These advantages enhance the manufacturability of the STI process module in terms of reducing the starting HDP film thickness,cutting down on etching and polishing times of RTE and CMP, respectively,and yielding better post-CMP within-die and within-wafer FOX uniformities.     

基于ICP的硅高深宽比沟槽刻蚀技术

介绍了电感耦合等离子体(ICP)刻蚀技术的基本概念。结合英国STS公司的STS multiplex ICP system刻蚀机,介绍了刻蚀机原理及刻蚀过程。对硅深槽刻蚀技术进行了分析,对其中Footing效应、Lag效应和侧壁光滑问题提出了优化方案,最后在实验的基础上得出了能够刻蚀出高质量硅深沟槽的刻蚀参数。     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。     

Time-domain optical wave propagation in disordered and nonuniformguiding structures

We formulate a time-domain numerical approach to optical wave propagation based on a locally one-dimensional implicit finite-difference approximation to the two-dimensional scalar wave equation and show how it can be used to study the nature of wave propagation in optical and optoelectronic devices with spatial nonuniformities and disorder. The technique is particularly well suited for the visualization of complex scattering and diffraction phenomena. We estimate the influence of interface roughness in semiconductor lasers with mirrors defined by etching processes as a function of a feature depth parameter and an in-plane correlation length. The reflectivity falls off exponentially with their product for small disorder yet remains close to its unperturbed value for the disorder scale attainable with the state-of-the-art etching technology. It is also shown how this approach can be applied to the design of an optically controlled heterojunction bipolar transistor, in which the Light enters from a lateral waveguide and must be absorbed in the base-collector depletion region     

双层侧壁保护的Si深槽刻蚀技术

提出了一种先进的ICP Si深槽刻蚀工艺。在"Bosch"工艺的基础上加以改进,以SF6/O2作为刻蚀气体,C4F8作为侧壁钝化气体,通过在刻蚀过程中引入少量的O2,使得在刻蚀Si深槽过程中侧壁形成由氧离子辐照产生的SiO2薄膜和CFx聚合物淀积产生的双层保护层,强烈保护Si槽侧壁不被刻蚀,保证了良好的各向异性刻蚀。同时,通过优化刻蚀和钝化的时间周期,进一步提高了刻蚀后Si槽的陡直度和平滑的侧壁效果。采用这种工艺技术可制作出满足台面晶体管、高性能梳状沟槽基区晶体管需要的无损伤、平滑陡直的Si槽侧壁形貌。     

Automated malfunction diagnosis of semiconductor fabricationequipment: a plasma etch application

A general methodology for the automated diagnosis of integrated circuit fabrication equipment is presented. The technique combines the best aspects of quantitative algorithmic diagnosis and qualitative knowledge-based approaches. Evidence from equipment maintenance history, real-time tool data, and incline measurements are integrated using evidential reasoning. This methodology is applied to the identification of faults in the Lam Research Autoetch 490 automated plasma etching system located in the Berkeley Microfabrication Laboratory     

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems

Debugging and speed-binning a fabricated design requires a pattern-dependent timing model to generate patterns, which static timing analysis is incapable of providing. To address these issues, we propose a timing analysis tool that integrates a pattern-dependent delay model into its analysis. Our approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a satisfiability (SAT) solver. We generate a critical path and input vectors that stimulate it, taking into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. The effectiveness and validity of the proposed methodology is illustrated through experiments on various benchmark circuits and comparisons directly with SPICE.     

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLKtrade) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Omega at 0.28 mumOslash with keeping large tolerance of misalignment up to 0.1 mum.     

硅槽刻蚀技术中的源气体选择

源气体及组分的选择是硅槽刻蚀技术的关键因素。本文介绍了刻蚀过程中源气体及组分对硅的作用方式，从刻蚀速率、侧壁钝化、损伤、刻蚀均匀性等方面分析比较了近年来所出现的几种硅糟刻蚀用源气体及组分。     

无中间层双大马士革中FSG刻蚀技术研究

随着超大规模集成技术的发展,芯片尺寸的日益缩小,铜作为连接材料的优越性日益显现。由于铜的反应生成物不具有挥发性,刻蚀很难实现。只有先在硅片上作好双大马士革结构,然后填入铜来实现铜互连。文章研究无中间层双大马士革中FSG刻蚀技术,将刻蚀过程细分为四步实施:VIA通孔刻蚀、BARC刻蚀、Trench沟槽刻蚀和阻挡层刻蚀(Nitride Remove),解决刻蚀过程中出现的主要问题。     

深硅槽开挖工艺

本文介绍了硅槽应用,即硅槽隔离和硅槽电容,对器件性能的改善。并介绍了硅槽隔离和硅槽电容的形成步骤及硅槽刻蚀剖面的形貌控制,CBrF_3刻蚀硅槽侧壁保护层的形成等等。     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

A novel trench capacitor enhancement approach by selective liquid-phase deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.     

用深反应离子刻蚀和介质填充技术制造具有高深宽比的超深电隔离槽

提出了一种利用深反应离子刻蚀(DRIE)和电介质填充方法来制造具有高深宽比的深电学隔离槽的新型技术.还详细讨论了DRIE刻蚀参数与深槽侧壁形状之间的关系,并作了理论上的阐述.采用经过参数优化的DRIE刻蚀深硅槽,并用反应离子刻蚀(RIE)对深槽开口形状进行修正,制造了具有理想侧壁形状的深槽,利于介质的完全填充,避免产生空洞.电隔离槽宽5μm,深92μm,侧壁上有0.5μm厚的氧化层作为电隔离材料.I-V测试结果表明该隔离结构具有很好的电绝缘特性:0～100V偏压范围内,电阻大于1011Ω,击穿电压大于100V.电隔离深槽被首次应用于体硅集成微机械陀螺仪上的微机械结构与电路之间的电气隔离与机械连接,该陀螺的性能得到了显著提高.     

Simulating the chlorine plasma etching profile of high-aspect-ratio trenches in Si

We simulate etching trenches in Si with a high (over 15) aspect ratio, i.e., the ratio between the trench depth and width in Cl₂ plasma in wide ranges of the ratio between the flows of Cl atoms and Cl⁺ ions (3–300) and ion energies (50–250 eV). We demonstrate that the trenches with a high aspect (HA) ratio (~20) and almost vertical walls can be formed at the maximum energies of E _i = 250 eV and R = 300. At the lower values of these parameters, etching an HA-ratio trench is accompanied by its narrowing, curvature, or bending. We discuss the origin of the HA-trench bending effect at small R values and a high energy of the incident ions.     

Numerical study of the implications of size nonuniformities in the performance of photonic crystal couplers using coupled mode theory

Photonic crystals (PCs) are a promising technology for the realization of high-density optical integrated circuits. PC-based couplers have been proposed as a compact means of achieving wavelength multiplexing and demultiplexing. However, the performance of such devices can be limited by fabrication imperfections such as rod size nonuniformities. In this paper, coupled mode theory (CMT) is applied in order to study the implication of the variation of the size of the rods. CMT can provide a useful insight in the effect of size variations, and unlike other numerical methods such as the finite difference time domain, it does not require excessive computational time. Using CMT, the relation between the size nonuniformities and the coupler's insertion loss and extinction ratio is analyzed. It is shown that even a small size variation of the order of 2%-3% can degrade the performance of the device.     

16通道微型集成滤光片制备技术的研究

多光谱成像光谱技术正在向光谱通道更多、集成度更高、体积小和重量更轻的方向发展,而用于分光的多通道滤光片是其关键光学元件,需要相应发展新型多光谱窄带集成滤光片制备技术.提出了组合刻蚀法布里-珀罗(F-P)滤光片间隔层的方法,将光学薄膜制备技术,离子束刻蚀技术与掩膜法技术相结合,形成新的多通道集成滤光片的制备方法.并在单个微型基片上,成功制备了集成16通道窄带线阵滤光片,获得的单元滤光片几何线宽为0.7mm,相对半峰全宽优于1.0%,透射峰定位精度优于0.25%.这一方法不但可满足集成度更高的滤光器件的要求,而且拓展了薄膜制备的方法.     

Reactive ion etching and characterization of p-silk ultra low-k film

Reactive ion etch (RIE) of p-SiLK, a spin-on polymer based ultra low-k (ULK) material with a k value of /spl sim/2.2 was characterized and its influence on electrical yield and dielectric breakdown is presented here. Material characterization was done using blanket films after curing and the effect of exposure to different conventional plasma etch gas mixtures was studied for surface composition, roughness and dielectric constant. Trench etch process was developed for 130-nm technology node for single damascene process integration. Dual hard mask approach was taken and two etch schemes viz., etching under hardmask and etching under photoresist were evaluated. In both schemes, trench etch profiles were near vertical and critical dimension (CD) control was within 10%. RIE lag and the carbon depletion at the sidewalls were found to be insignificant confirming acceptable etch process performance. Etching under photoresist scheme was found advantageous in terms of trench profile for isolated structures, reduced cycle time making the process cost effective and reduced post-CMP defects. However, from the comparison of electrical test results, etch under hardmask scheme showed higher electrical yield and better performance than etch under PR scheme. Although trench sidewalls were exposed to plasma during both schemes, sidewall damage did not contribute to overall leakage. The RIE process developed and the characterization results have confirmed the compatibility of material and RIE process for successful process integration.     

Thermal oxidation as a simple method to increase resolution in nanoimprint lithography

We introduce a simple thermal oxidation technique for decreasing feature sizes of nanoimprint lithography (NIL) masters. During oxidation, the dimensions of negative features are reduced (e.g., gaps become narrower), and the dimensions of positive features increase (e.g., lines become wider). We demonstrate that positive feature sizes can also be reduced after oxidation by selective etching of the oxide. We show that 74 nm gaps can be reduced to 10 nm and 226 nm lines can be narrowed to 55 nm. The reduction in feature size achieved in both positive and negative structures directly translates into increased imprint resolution, and we demonstrate improved resolution in a complete NIL pattern transfer using thermally oxidized NIL masters.