异构网络中多网络并行传输的网络选择算法

为了充分利用异构网络中的无线资源,提出了一种基于多网络并行传输的异构网络接入选择算法,该算法根据终端接收信号功率确定能够进行通信的无线网络,以这些无线网络的任意非空子集作为候选方案,计算各个方案对应的聚合属性,再根据吞吐量和功耗阈值条件限定候选网络方案,对这些方案建立多属性决策矩阵,采用基于用户偏好的逼近理想值排序法(TOPSIS)得到各个候选网络方案的效用函数值,从中选出与理想方案最接近的多网络接入方案。仿真结果表明该算法能有效改善用户服务质量,提高用户吞吐量,降低用户的单位吞吐量对应的功耗和费用,保证网络的负载均衡。      

基于最大化网络吞吐量的WMN信道分配算法

为了解决无线Mesh网络中的信道分配问题,提出了一种基于博弈论的信道分配算法.该算法将网络中每一个节点模型化为一个博弈者,每个博弈者的策略为信道的分配方案,并将整个网络的吞吐量作为效用函数的目标,效用函数的物理意义则是在给定流量需求矩阵下传输的成功率.博弈者通过相互博弈来优化收益函数以最大化网络吞吐量.通过NS2.34仿真分析得出,GBCA算法在收敛性、丢包率和吞吐量上都要优于当前的算法.     

一种基于MCS信息的白适应MIMO机制选择算法

文章讨论了在时变无线信道下多天线无线通信系统中MIMO机制的选择问题，并提出一种基于调制编码（Modulationand Coding Scheme，MCS）信息的MIMO机制选择方案。该方案通过对MCS信息进行统计和分析，自适应的选择MIMO机制以获得最大吞吐量。与已有MIMO选择方案相比，该算法不仅仍能准确地选择出合适的MIMO机制，而且易于实现，更容易应用于实际系统中。     

LTE-A系统中上行闭环功率控制的改进方法

针对传统闭环功率控制方案提出了一种新的上行功率控制策略,在原有闭环功率控制的基础上,针对不同区域的UE采用不同的发射功率控制方案。基于TDD-LTE仿真结果表明,改进算法在小区平均吞吐量和边缘UE吞吐量之间进行了很好的折中,相对于传统开环方案的边缘UE吞吐量平均提升约19.85%,相对于传统闭环方案的小区平均吞吐量平均提升约8.75%。     

OFDMA系统中功率分配新算法研究

通过对迭代注水算法的分析,提出了一种功率分配的新算法,该算法不需要多次迭代,并且能在一定功率约束的条件下,有效地提高系统吞吐量。给出了具体的算法实现步骤和复杂度分析,表明该算法复杂度明显低于迭代注水算法。最后,对该算法进行了仿真分析,并以信噪比为8 dB时为例,分析了两算法的吞吐量性能。仿真结果表明,在低信噪比环境中该算法对系统容量的改善更为显著,且所提算法的吞吐量性能完全逼近迭代注水算法。     

基于能量收集驱动和信道感知的CRN

针对能量采集器供电的认知无线电网络进行了研究。首先,在采用离散时间马尔可夫链的建模基础上,通过分析认知用户在收集到的能量包和电池容量的限制下有效地利用能量,以最大化当前时隙的吞吐量。然后,找到多个信道的最优感知顺序和对应于该感知顺序下信道的最优传输能量集,得到使认知无线电网络在多个时隙的预期吞吐量最大化的递归表达式。最后提出了一种基于该递归表达式实现最大化预期吞吐量的算法。仿真实验结果表明,所提出的方案相比于其他方案,不仅提高了认知无线电网络的吞吐量,而且降低了主信道上的平均碰撞比。     

多用户MIMO-OFDM系统中基于延时信道状态信息的自适应传输方案

为多用户MIMO-OFDM下行链路提出一种结合正交空时分组码与特征波束形成的传输方案,利用接收端反馈的延时信道状态信息进行自适应传输,使系统吞吐量最大.提出了自适应多用户子载波分配准则与相应的比特加载方法.仿真结果表明,该方案能充分利用具有时延的信道状态信息,相比非自适应系统,能有效提高系统吞吐量.还提出一种计算量极低的次最佳非迭代比特加载算法,仿真结果表明该算法引起的系统吞吐量损失很小.     

一种基于博弈论的无线mesh网络信道分配算法

无线mesh网络中的信道分配会极大地影响网络的性能。为了解决无线mesh网络中的信道分配问题,提出了一种基于博弈论的信道分配(GBCA)算法。该算法将网络中每一个节点模型化为一个博弈者,每个博弈者的策略为信道的分配方案,并将整个网络的吞吐量作为效用函数的目标,效用函数的物理意义则是在给定流量需求矩阵下传输的成功率。博弈者通过相互博弈来优化收益函数,以最大化网络吞吐量。并针对GBCA算法的不足,提出了一种改进算法———GBCA-TP算法。通过NS2.34仿真分析得出,GBCA算法和GBCA-TP算法在收敛性、分组丢失率和吞吐量上都要优于当前的算法。     

多小区边缘用户集中式资源分配策略

针对传统频率复用方案无法适应小区边缘负载变化的问题,提出一种多小区边缘用户集中式调度策略,可以在避免产生干扰的同时动态适应每个小区的负载分布情况,并结合一种基于匈牙利算法的资源分配算法来保证用户的速率要求和系统吞吐量。仿真证明,该方案相较其他方案在用户满意度和吞吐量上都有较大的提升。     

具有非线性能量收集的RIS辅助无线供电通信网络的吞吐量优化

为了提高无线供电通信网络（WPCN）的信息吞吐量及传能效率并实现系统可持续工作，研究可重构智能表面（RIS）辅助WPCN的吞吐量优化问题。采用非线性能量收集模型，并对RIS进行能量分配，通过联合优化RIS的反射相位和能量分配系数，基站的发射波束赋形，基站能量传输，下行能量传输和上行信息传输的时间分配，以最大限度提高网络用户信息传输的吞吐量。所考虑的优化问题的优化变量高度耦合，难以直接求解。提出基于分块优化、松弛变量引入和半正定松弛方法的高效算法求解该问题。仿真结果表明，与现有的基准方案对比，所提算法能显著提高系统吞吐量和可靠性。     

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and Data Flow Graph transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18 μm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.     

Cost-Efficient SHA Hardware Accelerators

This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. Compared to commercial cores and previously published research, these figures correspond to an improvement in throughput/slice in the range of 29% to 59% for SHA-1 and 54% to 100% for SHA-2. Experimental results on hybrid hardware/software implementations of the SHA cores, have shown speedups up to 150 times for the proposed cores, compared to pure software implementations.      

5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-holdamplifier

A 5 V, 100 MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8 bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous paper (see Int. J. Electron., vol. 78, no. 5, p. 907-910, 1995), the proposed SHA is implemented by an open-loop structure using the `gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

A fast approach for bitcoin blockchain cryptocurrency mining system

The growth of the blockchain-based cryptocurrencies has attracted a lot of attention from a variety of fields, especially in academic research. One of them is Bitcoin, the most popular and highest valued cryptocurrency on the market. The SHA256 is the main processing part in Bitcoin mining, to date the difficulty of which is extremely high and still increases relentlessly. Hence, it is essential to improve the speed of the SHA256 cores in the Bitcoin mining system. In this paper, we propose a two-level pipeline hardware architecture for the SHA256 processing. The first-level pipeline helps the system reduce the number of operating cycles. Besides, the maximum frequency of the system is boosted by the second-level pipeline. The proposed hardware is implemented on FPGA Xilinx Virtex 7-VC707 (28 nm technology). The mining hash rate using the proposed pipeline SHA256 cores reaches 514.92 MH/s that improves 2.4 times compared to the FPGA based conventional technique. The throughput of SHA core of current study is 296.108 Gbps that is 240 times higher compared to the standard technique. The proposed architecture is also implemented in an ASIC design using ROHM 180 nm CMOS technology, which resulted in a throughput of 69.28 Gbps that is 18 times higher than that of conventional work implemented in Intel 14 nm process.     

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

To reduce power dissipation, the input sample-and-hold amplifier (SHA) is eliminated in a pipelined analog-to-digital converter (ADC) with nested background calibration. The nested architecture calibrates the pipelined ADC with an algorithmic ADC that is also calibrated. Without an input SHA, a timing difference between the sampling instants of the two ADCs creates an error that interferes with calibration of the pipelined ADC. This problem is overcome with digital background timing compensation. It uses a differentiator with fixed coefficients to build an adaptive interpolator. With a 58-kHz sinusoidal input, the 12-bit 20-Msample/s pipelined ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.2 dB, a spurious-free dynamic range (SFDR) of 80.3 dB, and an integral nonlinearity (INL) of 0.75 least significant bit (LSB). With a 9-MHz input, the SNDR is 64.2 dB, and the SFDR is 78.3 dB. About 2 million samples or 0.1 s are required for convergence. The prototype occupies 7.5 mm² in 0.35-mum CMOS and dissipates 231 mW from 3.3 V, which is 23 mW less than in a previous prototype with the input SHA.     

SHA1 IP的设计及速度优化

论文简要介绍了SHA1算法的基本流程,并给出了一种硬件实现方案,文中着重介绍了提高IP的工作速度所采用的三种速度优化方案,并在文章的最后对速度优化的结果进行了比较,可以看出通过优化IP的工作速度得到了显著的提高。     

基于采样保持器的滤波电路研究

研究和探讨了基于采样保持器的滤波电路———采样保持滤波SHF电路,即利用采样保持器的采样保持特性,对某些特定波形模拟信号进行滤波处理。理论分析表明,这种SHF电路是可行的;实验仿真也证实,相对于传统的有源RC滤波电路,这种SHF电路具有更优异的处理效果。SHF电路结构在一定程度上解决了有源RC滤波电路对某些特定信号处理不足的问题。     

一种在智能卡芯片中实现SHA-1算法的方法

SHA是由美国国家安全局(NSA)设计的安全杂凑算法.该算法主要应用在通讯完整性验证以及数字签名认证领域.以面积优化为目标,从系统设计入手到模块级设计,以具体设计为实例,在智能卡芯片中以较小的面积代价实现了SHA-1算法,对于类似的杂凑算法设计具有普遍的参考价值.     

A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bitsat Nyquist

A CMOS subranging analog-to-digital converter (ADC) incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal ill-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADC's with differential inputs and significantly better than those with single-ended inputs. The typical maximum differential nonlinearity is ±0.4 LSB, and the maximum integral nonlinearity is ±0.55 LSB without trimming or calibration. With an ADC power of 55 mW plus an SHA power of 20 mW from a 5-V supply, the active area is 1.6 mm² in a 0.5-μm double-poly, double-metal CMOS technology