Wishbone总线交易级建模

交易级建模在系统功能建模和验证方面可以增快速度,也可以加速仿真的速度并允许在高层次抽象中研究和确认设计中可供选择的模块.针对Wishbone片上总线协议,依据SystemC中接口方法调用的基本原理和交易级建模的方法,完成了Wishbone总线中共享总线的交易级建模,结果表明SystemC适合在交易级建模系统的行为和通信,交易级建模在仿真速度方面具有优势.     

通信系统中SystemC可重用验证平台的设计

文章以SystemC为验证语言的通信系统的可重用验证平台的设计思路,通过层次化设计,将验证平台划分为4个层次:用户层、配置管理层、总线功能模型层和待测设计层.介绍了各层接口的通信方式,着重介绍了用户层模块、算法模块、端口模块、激励产生模块、总线功能模块以及结果比较模块重用设计方法,依照此方法能快速高效地搭建可重用的验证平台.     

基于SystemC的事务级建模研究

探讨了基于SystemC的事务级建模方法,并结合SoC片上总线,以DVB-C数字电视机顶盒给出建模实例.基于SystemC的SoC总线模型有效克服了SoC软硬件协同设计的时间瓶颈问题,提高了开发效率,缩短了产品的开发周期.目前该系统正处于板级调试过程中.     

SystemC在Turbo码实现和验证中的应用

在简述System C的设计方法和流程的基础上,针对SystemC在硬件芯片系统级设计和寄存器传输级设计的特点,以Turbo编码器为对象和开发目的,研究了SystemC基于寄存器传输级设计的可实现性,利用SystemC的模块化功能,通过分析Turbo编码器的结构与信号流图,进行建模仿真直到最后完成划分硬件模块与编程并在FPGA完成其实现与验证,充分证明了SystemC完全适用于基于寄存器传输级设计的IC应用.此外,此设计将系统级设计与寄存器传输级设计的工作合二为一,大大节省了开发的流程时间.     

可重构专用处理器周期精确建模

介绍了一种基于SystemC的可重构专用处理器核周期精确建模.该模型采用模块化设计,基于SystemC事务级建模,将运算功能和通信功能分开,模块之间的通信通过函数调用来实现.通过该模型,为可重构专用处理器核提供一种仿真验证平台,与传统RTL验证方法相比,大大提高了可重构专用处理器核的仿真验证效率.     

基于SystemC的时钟周期精确交易级建模及通信细化

交易级建模通过提高建模抽象层次,加快了系统建模和仿真的速度。针对AMBA AHB协议,采用Sys-temC语言,进行了交易级建模及通信细化。结果表明,由于抽象层次部分结合了BCA(bus cycle-accurate)级描述,使得到的交易级模型包含了更多时间/协议信息,同时保留了速度优势,有利于前期验证和系统开发。而之后进行的通信细化,将抽象通道转化为模块实体和端口,对于最终RTL级实现具有重要意义。     

基于SystemC的周期精确级DSP处理器建模

针对高级语言做处理器建模在模型精度方面的不足,本文探讨了一种基于SystemC的周期精确级DSP处理器建模方法.在分析各流水段功能的基础上,结合SystemC的语言结构特点,对流水级内各功能模块进行了抽象建模.该模型能够精确地模拟处理器指令的执行情况,对软件算法的设计优化和处理器微结构的探索具有一定的参考价值.     

NoC架构片上多处理器系统性能探索

采用SystemC建模和仿真环境建立了一教NoC系统级仿真平台,设计了3个实验分别用于建模3种典型应用(低计算/通信比、高计算/通信比和非独立任务),以定量模拟的方法对NoC架构MPSOC性能进行了详细的调研,并将其结果与总线架构MPSoC进行了对比分析.实验结果显示:NoC系统加速比与处理器数目呈线性关系,不受规模的影响,而总线系统则明显受到处理器数目的限制;共享存储资源成为NoC系统性能提升的限制,但可以通过采用分布式存储策略得到解决,而总线系统却无法克服其共享总线通信瓶颈.因此,在系统规模较大(N>12)时推荐采用NoC体系结构.     

片上网络的SystemC建模研究

为了实现软硬件协同设计和提高仿真速度的需求,采用SystemC语言的建模方法,通过对片上网络体系结构的研究,提出了一种片上网络的建模方案,并对一个mesh结构完成了SystemC的建模设计。该模型可在系统级和寄存器传输级上使用同一个测试平台,且具有仿真速度快的特点,达到了设计要求。     

SystemC在现代通信ASIC设计中的应用

SystemC作为一种新兴的SoC设计语言，正在成为现代通信ASIC设计的重要工具之一。文章对SystemC以及它在通信ASIC设计中的应用从算法级和系统结构级两个方面进行了研究，主要内容包括应用SystemC进行通信ASIC算法的定点性能分析和算法优化，对SystemC实现的算法模型进行时序封装，进行系统结构级仿真验证的方法。研究表明，使用SystemC进行通信ASIC算法和系统结构的设计验证．能够大大提高现代通信ASIC设计的工作效率和产品质量。     

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.     

可重构处理器阵列的系统级建模研究

由于粗粒度可重构体系结构设计空间复杂,设计满足应用需求的CGRA需要建立系统级仿真模型进行性能评估．文中提出一种可重构处理器阵列的系统级模型,使用SystemC事务级语言实现建模．模型采用多层互连网络结构实现任意2个处理器间的通信,并且处理器的资源能够通过参数快速地进行配置．仿真实验表明,模型适用于应用算法到粗粒度可重构体系结构映射的模拟仿真．     

一种动态可重构协处理器参数化系统级模型研究

提出了参数化系统级模型.该模型不依赖于具体结构,以任务布局与重构处理分离的两级结构处理任务调用,通过参数方式实现不同设计方案的硬件结构和布局算法的配置.采用SystemC语言对模型进行了建模验证,仿真结果表明,通过指定上下文的下载、配置和执行等时间开销参数,在系统级设计空间探索中,能很好地模拟动态重构协处理器.     

SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC

During early design phases performance evaluation becomes increasingly important since major system-level decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, affect the quality of the design significantly. Quantitative analysis is hard to achieve due to growing complexities, heterogeneity, and concurrency of modern embedded systems. We propose the use of multiclass queuing networks during the specification phase of the design flow for modeling data-flow oriented systems. Starting from an executable high-level queuing model our evaluation framework SystemQ¹ enables successive and systematic refinement of behavior and structure towards established TLM and RTL models based on SystemC. We demonstrate why SystemQ’s multiclass queuing networks are a natural and feasible abstraction for evaluating network processing platforms. In particular we reveal the impact of scheduling policies on the Quality-of-Service, such as the residence time of network traffic in the system. In our case study, we show how stepwise refinement can reduce memory and latency bounds by up to two orders of magnitude and how the choice of only one queuing discipline can affect these properties. The investigated simulation models run in the range of 1 : 100 to 1 : 1 of real-time on a common off-the-shelf Linux PC.     

Behavioral Modeling and Simulation of Mixed-Signal System-on-a-Chip using SystemC

We describe an efficient software framework for rapid behavioral modeling and simulation of mixed-signalSystem-on-a-Chip (SoC). The framework is based on the SystemC C++ class libraries and has beenproven to be a very effective tool for exploring different system-level architectures in the early stages of thedesign process. We also present the results of three case studies where we have used the framework: a 10-bit, 60Mega-sample/s pipelined ADC, 14-bit, 100 Mega-sample/s pipelined ADC with background calibration, and aCMOS camera-on-a-chip.     

A methodology aimed at better integration of functional verification and RTL design

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.     

DVD伺服控制芯片的系统级仿真环境的构造

文章介绍了DVD伺服控制芯片的系统级仿真环境的构造，包括仿真模型的建立和采用的仿真管理方法。仿真结果显示，该系统级仿真环境能准确地模拟各功能模块之间的交互，在该仿真环境下能快速地对RTL源代码进行调试。     

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.