Acquisition Behavior of the Cross-Coupled Phase-Locked Loop FM Demodulator

In this work, the acquisition behavior of a cross-coupled phase-locked loop (CCPLL) FM demodulator capable of suppressing cochannel and adjacent channel interferers is examined. This novel detector consists of two phase-locked loop (PLL) demodulators interconnected in such a manner as to permit one PLL to lock onto and track the stronger received signal, while the other loop tracks and demodulates the weaker of two received signals. The demodulator has two separate outputs, namely, the outputs of each PLL, and thus possesses the capability of demodulating both the stronger as well as the weaker received signals even though they are cochannel and share the same frequency band. The transient response of the CCPLL system is obtained using computer-aided analysis of the defining coupled nonlinear differential equations. From these results, steady-state "stability regions" are derived which reveal that range of loop parameters where successful separation and demodulation of the received cochannel signals is assured. The CCPLL receiver has numerous technological applications in suppressing unintentional or intentional CW, AM, FM, and AM/FM interferers. Experimental results demonstrating such potential are included.     

Maximum A Posteriori Estimator for Suppression of Interchannel Interference in FM Receivers

In this paper an FM detector capable of suppressing the degradation in receiver performance due to the presence of an interfering signal is presented. Optimum receiver structures based on maximum-aposteriori estimation procedures are first derived and then a practical demodulator based on the optimum receivers is examined. The receiver consists of two phase-locked loops (PLL) interconnected in a manner to permit one PLL to lock onto and track the Stronger received FM signal while the other loop tracks the weaker of the two received FM signals. The detector has the capability of demodulating both the desired received FM as well as the interferer even for the case when both signals are co-channel. Experimental results demonstrating such capability even in the presence of strong input Gaussian noise are presented.     

Phase-Locked Loop Coherent Combiners for Phased Array Sensor Systems

Phase-locked loops (PLL's) may be used to implement signal combiners which coherently sum multiple signals from an array of sensors. In each combiner channel, the sensor signal is simultaneously downconverted to an intermediate frequency (IF) signal and phase-locked to an appropriately generated reference signal by a "long-loop" PLL. This loop maintains a nominal 90° phase difference between the IF signal and the reference signal irrespective of phase of the channel input (sensor output) signal. The channel IF signals are summed to generate the combiner output signal. The reference signal may be a locally generated sine wave or a delayed version of the combiner output signal. Imperfect phase control and, thus, imperfect signal combining results when noise voltages are associated with the channel signals. In this paper, a lincarized model of a PLL coherent combiner is developed. This model applies when the desired channel signals are equal amplitude and angle modulated; the channel noise voltages are equal level, Gaussian distributed, and independent; and the combiner phase errors are appropriately small. This model is then used to derive equations for the variance of differential phase errors associated with combiner operation and to show the effect of these phase errors on the average power in the combiner output signal. Relevant experimental results from a four-channel combiner are compared with the performance predicted by the linear model.     

An architecture of high-performance frequency and phase synthesis

Frequency synthesis has many applications in today's commercial electronic and telecommunication system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This architecture is used to generate a signal of any desired frequency in a certain range from multiple reference signals with same frequency but different phases. These reference signals may come from a voltage-controlled oscillator (VCO) which is close looped with a reference clock by a phase-lock loop (PLL). This architecture provides some unique features, superior quality, and ease of implementation. In some cases, the synthesized frequency is time-average frequency. The signal can be treated as a carrier signal frequency modulated by another signal. Various phase-shifted versions and duty cycle versions of this signal can also be generated from this architecture. This architecture also has direct application to spread spectrum clock generation     

一种自偏置锁相环电路的分析与测试

自偏置锁相环电路结构自提出以来便受到了极大的关注,人们普遍认为其可以改善锁相环的相位噪声。为了验证这种结构能否改善传统锁相环电路的相位噪声性能,根据锁相环的基本理论设计并实现了一种可进行重新配置的锁相环电路结构,电路中的锁相环结构可以在传统锁相环、自偏置锁相环和普通偏置锁相环之间进行切换。使用信号源分析仪分别测试得到了这3种结构的相位噪声性能：自偏置锁相环的带内相位噪声比普通锁相环恶化了约6 dB,而采用普通偏置锁相环使环路等效分频比减小5的相位噪声比普通锁相环改善了约14 dB。理论与测试结果均表明,自偏置锁相环和普通锁相环相比,环路反馈回路中的分频比并没有有效降低,因此自偏置锁相环的相位噪声性能并没有得到改善。     

Angle Modulation Limits of a Noise-Free Phase Lock Loop

Methods are presented for determining the modulation limits of phase lock loop (PLL) FM demodulators. These limits establish the maximum deviation that the PLL can support (i.e., remain "inlock") based on the loop design parameters. The modulation limits are derived from experimental data on first and second order loops using sinusoidal and Gaussian noise modulation. The analysis of each PLL is broken into two regions, low frequency and high frequency modulation. It is shown that the deviation limit remains constant with modulation frequency for a first order loop in the low frequency region. In the high frequency region the deviation limit increases with increasing modulation frequency for both first and second order loops. The deviation limit in a second order loop increases with decreasing modulation frequency in the low frequency region and is a function of the loop damping.     

利用矢量跟踪环路的欺骗干扰检测与抑制方法

欺骗干扰的信号模型与真实卫星信号相似,具有很强的隐蔽性。近年来欺骗干扰不断威胁GPS系统因此受到了国内外学者的广泛关注。生成式欺骗干扰的延迟和功率具有可控性和变化性,因此隐蔽性和危害性更强。针对该问题,本文在欺骗干扰来向与真实卫星信号来向未知的前提下,结合阵列天线技术与矢量跟踪环路,提出一种基于矢量跟踪环路的欺骗干扰检测和抑制方法。该方法首先根据矢量跟踪环路的预测参数重构基于远滞后码的参考信号;其次根据接收信号与参考信号的相干累加结果构造欺骗干扰检测模型;然后根据阵列接收信号与参考信号的相干累加结果估计协方差矩阵;最后根据协方差矩阵中最大特征值对应的特征向量估计欺骗信号的特征向量,并根据该特征向量构造正交投影矩阵抑制欺骗干扰。理论分析和仿真实验得出了本文提出的算法具有较好的抗欺骗干扰性能。      

Estimating and interpreting the instantaneous frequency of asignal. II. Algorithms and applications

For pt.I see ibid., vol.80, no.4, p.520-38 (1992). The concept of instantaneous frequency (IF) is extended to discrete-time signals. The specific problem explored is that of estimating the IF of frequency-modulated (FM) discrete-time signals embedded in Gaussian noise. Well-established methods for estimating the IF include differentiation of the phase and smoothing thereof, adaptive frequency estimation techniques such as the phase locked loop (PLL), and extraction of the peak from time-varying spectral representations. More recently, methods based on a modeling of the signal phase as a polynomial have been introduced. These methods are reviewed, and their performance compared on both simulated and real data. Guidelines are given as to which estimation method should be used for a given signal class and signal-to-noise ratio (SNR)     

QPSK扩频调制信号载波跟踪环路设计

扩频接收基带通常需要载波跟踪环来完成本地载波与接收信号载波的同步,科斯塔斯环是常用的非相干载波相位跟踪环,具有较好的鉴相特性。本文基于常规的单路单载波解调的科斯塔斯环原理,对科斯塔斯环做了改进,提出了对双通道平衡QPSK扩频基带所用载波跟踪环科斯塔斯环的改进方法,并推导出环路误差鉴相信号,用Matlab进行了仿真实验,结果证明利用本环路可实现载波稳定跟踪。     

高动态GPS接收机跟踪环路设计与实现

为了解决高动态环境下GPS信号跟踪问题,讨论了跟踪环路类型和参数的选择策略,给出了一组适合高动态应用的环路参数,分析了基于开环频率估计和2阶FLL(Frequency Lock Loop)辅助3阶PLL(Phase Lock Loop)的高动态环境下快速的捕获转跟踪方法,给出了在由FPGA和DSP组成的硬件平台上的具体实现,利用GPS信号模拟器对所设计的跟踪环路的动态性能进行了验证。测试结果表明所设计的高动态跟踪环路能够承受60g视距动态应力。     

锁相环路的特性及其应用

锁相环路是一种以消除频率误差为任务的自动控制电路,由鉴相器、环路滤波器和压控振荡器组成,具有自动跟踪、锁定后没有频差、良好的窄带特性和易于集成的特点,广泛应用于倍频、分频和混频以及滤波、模拟数字信号的调制和解调、信号检测和接收、频率合成等许多技术领域,是现代电子产品中非常重要的部件。对环路结构和特性进行分析及锁相环路在不同领域的应用进行介绍,通过框图进一步阐述相应内容,使广大读者进一步认识锁相环路及其相应的产品。     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

Detection of Digital FSK and PSK Using a First-Order Phase-Locked Loop

A classical problem in digital frequency-shifted keyed (FSK) demodulation is the evaluation of the bit error probability performance when an estimator-correlator that incorporates a phaselocked loop (PLL) is employed. Although some attention has been devoted to this problem in the past, an accurate account of the mechanism which produces decision errors has not yet been advanced. This paper examines a special case, viz., a first-order PLL preceded by a wideband IF filter, of the above problem using a new approach which is based upon the renewal Markov process theory and the Meyr distribution. In particular, the ad hoc approach of invoking the Gaussian assumption on the decision variable and patching it with a correction term based on Rice's click theory is not used. Rather, the effective noise is properly characterized by unfolding the renewal Markov process associated with the loop phase error. As a slight extension of the results, the performance of the above PLL detector operating on low data rate PSK is given and demonstrated to be approximately 3 dB superior to that of FSK reception. The theory and analysis presented herein apply to the special case where the bandwidth of the IF filter preceding the first-order PLL is required to be several times the data rate because of frequency uncertainties due to channel Doppler and oscillator instabilities, but the frequency deviation to data rate ratio may be chosen small (if desired) to optimize system error probability performance. In addition to presenting results for the case where the oscillator instabilities are assumed absent and channel Doppler is prefectly tuned out at the receiver oscillator, the effects of small residual Doppler on bit error probability performance is considered. In all cases tested, excellent agreement was obtained between theory and computer simulation results.     

Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop

The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. In this brief, a new CP with good current matching characteristics is proposed. By using a simple gain-boosting circuit, good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.8-2.2 V and 0.5-1.2 V on 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS processes, respectively. The proposed CP circuit is simulated and verified by HSPICE with 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS parameters     

GPS接收机载波跟踪环路设计

载波跟踪环路设计是GPS接收机中的关键技术,载波环鉴别器的类型确定了跟踪环的类型,为了有效地防止因为数据跳变引起的鉴别误差,并且使其频率鉴别范围大,精度高,采用一种二阶锁频环（FLL）辅助三阶锁相环（PLL）的方法。通过Matlab仿真载波环路比较了两种鉴频和鉴相算法的性能。结果表明,该方法鉴别范围大,精度高,切实可行。     

低载噪比GPS信号载波跟踪环路滤波算法

抑制锁相环（PLL）中的抖动噪声对于连续精确跟踪低载噪比GPS信号具有重要意义。本文设计了一种基于Kalman滤波理论的PLL模型用于处理GPS软件接收机中的弱载波信号。该模型通过去相关模型误差噪声和测量噪声,使PLL具有更小的过冲和噪声干扰的载波相位差和多普勒频移的正确估计,保持了PLL对GPS信号的有效跟踪。最后,通过仿真实验说明了基于Kalman滤波器的PLL的可行性。     

四相鉴频器辅助的高动态BOC信号载波跟踪

叉积鉴频器的输出频率范围比较窄,捕获信号以后的多普勒频偏可能不在其跟踪范围内。针对此问题,提出了使用四相鉴频器( FQFD )算法辅助已经成型的二阶锁频环加三阶锁相环模型。首先,利用四相鉴频器的非线性特性将接收信号频偏大步长牵引到较低范围,然后使用锁频环消除其大部分动态性,最后利用锁相环跟踪精度高的特点实现高动态二进制偏移载波( Binary Offset Car-rier,BOC)信号载波的快速准确跟踪。在分析各跟踪模块算法的基础上,讨论了其本身的热噪声误差、动态适应力以及最优带宽等相关问题,理论分析和仿真结果验证了该方法比原有跟踪算法提高了300 Hz左右的鉴频范围,并且跟踪效果良好。     

锁相环CD4046的应用设计及研究

讨论锁相环的原理及应用,设计基于锁相环CD4046的锁相频率合成器和鉴频电路,对电路作了实验验证和分析。该设计电路简单实用。能较好地说明锁相环的应用设计过程及优势,利于对锁相环应用的研究。     

Phase-Locked Loop Performance in the Presence of CW Interference and Additive Noise

This paper presents the results of an investigation concerning the performance degradation of a phase-locked loop (PLL) due to continuous wave (CW) interference and additive white Gaussian noise. The performance measures evaluated include the probability density function (pdf) of phase error and the cycleslipping rate. The measures are characterized in terms of the ratio of interference to the desired signal power and the loop signal-to-noise ratio. Since the interference term in the loop phase error signal is periodic, the conditional pdf of the phase error process is cyclostationary. A Fourier series expansion is applied as an approach to obtain a solution to the cyclostationary process. Linear performance results are derived and compared to the analytic results.     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。