A novel comparator featured with input data characteristic

Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators.     

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors

As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology     

一种新型自复式过电压、欠电压保护器的设计

利用555集成块设计了一种新型自复式过电压、欠电压的低成本保护器。采用两个电压比较器构成双限电压比较器电路,具有判断电压准确误差小的特点,对于电压误差要求较高的仪器有很好的保护作用,同时还能根据负载的不同要求容易改变上限电压和下限电压。采用555触发器构成的延时电路,具有延时时间准确判断无误的特点,能根据负载的不同要求改变延时时间。采用控制继电器实现供电和断电的方法,很好地实现了保护器与负载的隔绝,使用更方便、安全。     

高速CMOS闪烁型模数转换器中的误差源研究

对高速CMOS闪烁型模数转换器中的六种误差源进行了研究.每个误差源会潜在的限制模数转换器的线性度和信噪比.这些误差源包括基准电压的非理想因素、前置放大器引入的输入有关的时间延迟、比较器的回程噪声、时钟抖动与分布特性、温度计码中的火花码、比较器的亚稳态.在每种误差源研究的基础上,给出了相应的电路解决技术,使得吉赫频率范围中等分辨率的CMOS闪烁型ADC成为现实.     

RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

An analog synchronous mirror delay for high-speed DRAM application

An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-μm double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1×0.7 mm² . An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps±200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input     

低延迟低电压电流比较器

设计了一种基于改进共源共栅电流镜的CMOS电流比较器,该比较器在1 V电压且电压误差±10%的状态下都正常工作,同时改进后的结构能够在低电压下取得较低的比较延迟。电路的输入级将输入的电流信号转化为电压信号,电平移位级的引入使该结构能够正常工作在不同的工艺角和温度下,然后通过放大器和反相器得到轨对轨输出电压。基于SMIC 0.18μm CMOS工艺进行了版图设计,并使用SPECTRE软件在不同工艺角、温度和电源电压下对电路进行了仿真。结果表明,该电路在TT工艺角下的比较精度为100 nA,平均功耗为85.53μW,延迟为2.55 ns,适合应用于高精度、低功耗电流型集成电路中。     

A low propagation delay dispersion comparator for a level-crossing AD converter

This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.     

A 32 kbyte integrated cache memory

The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability     

一种基于时延配置表的FPGA静态时序分析算法

为减小现场可编程门阵列(FPGA)关键路径的延时误差,提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响,同时在时序分析过程中,通过分析路径始节点与终节点的时钟关系,实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明,与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比,关键路径延时的相对误差平均减少了8.58%和6.32%,而运行时间平均仅增加了19.96%和9.59%。     

A novel method for multipath routing using cross layer approach in vehicular adhoc networks

Vehicular Adhoc Network (VANET) is playing a vital role in recent research. Designing an effective routing protocol for VANET is a challenging task as the VANET nodes move very fast. The design of the routing protocol normally is particular to the specific topology. This paper proposes CLMR, a multipath routing protocol based on cross layer design and also using Redundant Array Inexpensive Disks (RAID). Cross layer is designed among application, network, Media Access Control, and physical layers. It is employed to reduce the end to end delay in network, and RAID is used to minimize the number of re‐transmissions. Three variations of RAID 1 are implemented—Distributed Parity along Single path, Double Distributed Parity, and Distributed Parity among Multiple paths. Multipath routing protocol based on cross layer‐Distributed Parity along Single path recovers 1 packet loss per parity packet along the corresponding path, CLMR‐Double Distributed Parity recovers 2 packets per parity packet along the corresponding path, and CLMR‐Distributed Parity among Multiple paths recovers the packets of the failed path. The evaluation is carried out to test the Quality of Service parameters‐end to end delay, throughput, packet delivery ratio, and number of retransmissions. The results projected show that the CLMR performs better when compared with the legacy protocol Adhoc On‐demand Multipath Distance Vector Routing.     

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.     

基于济南地区的对流层湿延迟模型对比研究

为提高济南地区对流层路径湿延迟测量精度,改善此地区大气折射修正误差,进一步提高该地区导航、定位、测控雷达等无线电测控系统的精度和性能,文中以济南站全球电信系统（Global Telecommunications System,GTS）探空数据计算的天顶湿延迟、斜路径湿延迟为比较基准,比较分析了利用Marcor技术、Hopfield模型、Ifadis模型所得到的对流层天顶湿延迟和斜路径湿延迟.比较结果表明:利用Marcor技术所得到的天顶湿延迟和斜路径湿延迟比其他模型得到的精度高,且仰角越低,斜路径湿延迟相对精度越高.这表明Marcor技术在济南地区具有很强的适用性,是获取高精度对流层湿延迟有效手段之一,有望逐步取代气象探空技术在工程中应用.     

激光脉冲测距双阈值时刻判别技术研究

在脉冲式激光测距技术中,回波信号幅度和上升时间变化引起的时间晃动误差是影响激光测距精度的主要因素之一.针对时间晃动误差带来的测距精度低的难题,在分析了时间晃动误差和总结一般时刻判别技术的基础上,设计了由高速比较电路,单稳态脉冲展宽电路、脉冲延时电路和快符合电路组成的双阈值时刻判别电路,并对电路进行了误差分析.与一般的时...     

On the Exploitation of Narrow-Width Values for Improving Register File Reliability

Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft errors induced by high-energy particle strikes. Since the register file is in the critical path of the processor pipeline, any reliable design that increases either the pressure on the register file or the register file access latency is not desirable. In this paper, we propose to exploit narrow-width register values, which present the majority of the generated values, for making a duplicate of the value within the same data item; this in-register duplication (IRD) eliminates the requirement for additional copy registers. The datapath pipeline is augmented to efficiently incorporate parity encoding and parity checking such that error recovery is seamlessly supported in IRD and the parity checking is overlapped with the execution stage to avoid increasing the critical path. A detailed architectural vulnerability factor (AVF) analysis shows that IRD significantly reduces the AVF from 8.4% in a conventional unprotected register file to 0.1% in an IRD register file. Our experimental evaluation using the SPEC CINT2000 benchmark suite also shows that IRD provides superior read-with-duplicate (RWD) and error detection/recovery rates under heavy error injection as compared to previous reliability schemes, while only incurring a small power overhead.      

一种嵌入式SIMD协处理器地址产生器的设计

文章介绍了一种新的嵌入式SIMD协处理器地址产生器.该地址产生器主要完成地址计算和协处理器指令的场抽取功能.为了提高协处理器的性能,地址产生器中设计了新的传送路径.该传送路径能够不通过地址产生器中的ALU而把数据送入寄存器中,这个传送路径能够减少ldN指令的一个延迟周期.在SMIC0.18微米标准库单元下,该地址产生器的延迟能够满足周期为10ns的协处理器.     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

Error protection for progressive image transmission over memorylessand fading channels

Product channel codes are proposed to protect progressively compressed and packetized images for noisy channels. Within packets, the product code uses the concatenation of a rate-compatible punctured convolutional code and an error detecting parity check code. Across packets, Reed-Solomon codes are used. Benefits include flexible choice of delay, adaptability of error protection level (i.e., unequal error protection), and scalable decoding complexity. The system outperforms the best known image coders for memoryless channels and performs well on fading channels     

基于分布式奇偶校验码的低复杂度极化码SCLF译码算法

针对极化码串行抵消列表比特翻转(Successive Cancellation List Bit-Flip, SCLF)译码算法复杂度较高的问题,提出一种基于分布式奇偶校验码的低复杂度极化码SCLF译码(SCLF Decoding Algorithm for Low-Complexity Polar Codes Based on Distributed Parity Check Codes, DPC-SCLF)算法。与仅采用循环冗余校验(Cyclic Redundancy Check, CRC)码校验的SCLF译码算法不同,该算法首先利用极化信道偏序关系构造关键集,然后采用分布式奇偶校验(Parity Check, PC)码与CRC码结合的方式对错误比特进行检验、识别和翻转,提高了翻转精度,减少了重译码次数。此外,在译码时利用路径剪枝操作,提高了正确路径的竞争力,改善了误码性能,且利用提前终止译码进程操作,减少了译码比特数。仿真结果表明,与D-Post-SCLF译码算法和RCS-SCLF译码算法相比,所提出算法具有更低的译码复杂度且在中高信噪比下具有更好的误码性能。     

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.