MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6.91kHz/g.     

1种用于TPMS的新型环振式数字压力传感器

研制了一种新型环振式数字压力传感器,它可应用于汽车轮胎压力监测报警系统(TPMS).采用硅薄膜上的PMOS环形振荡器作为压力敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、温度系数低、灵敏度高以及制作工艺简单等特点.分析并设计了压力传感器的环形振荡器电路、混频器电路、物理结构.分析了环形振荡器的频率特性、环形振荡器的谐振频率与压力的关系,以及制作工艺,并制作了样品,其灵敏度为5.12 kHz/Bar.     

以混频器作为信号处理单􀀂 元的环振式压力传感器

提出了一种新的环振式数字压力传感器，它采用做在硅梁上的MOS环形振荡器作为敏感元件，两个反方向变化的环形振荡器的输出信号通过集成在片内的混频器实现频率相减，分析了环形振荡器的频率特性，以及环形振荡器的谐振频率和压力的关系，分析并设计了压力传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺，并制作了样品，其灵敏度为1．52kHz／kPa。     

具有频率输出的硅压力传感器

本工作提出的具有频率输出的硅压力传感器是建立在CMOS环形振荡器基础上的,该环形振荡器是放置在传感器芯片的薄膜上的.由于压力压阻效应,施加的压力在薄膜上产生的机械应力改变了环形振荡器中MOSFET载流子的迁移率,从而MOSFET的漏电流及相应的环振频率成为压力的函数.     

一种基于电流舵逻辑的环形振荡器

文章分析了电流舵逻辑门的动/静态特性.为了比较电流舵环形振荡器和普通数字反相器环形振荡器,采用1.2 μm标准CMOS工艺,设计并制作了两种环形振荡器.仿真和试验结果表明,电流舵环形振荡器具有低噪声和频率不随电压变化的特点,但其功耗比较大,适合于噪声要求高而功耗要求不高的电路.     

基于无源RFID的集成加速度传感器设计

针对射频识别技术(RFID)迅猛发展的需求,采用0.35μm CMOS工艺设计并制造了一种集成加速度传感器。加速度传感器单元利用基于深反应离子干法刻蚀的体硅正面加工工艺,在经过标准IC工艺之后进行两步干法刻蚀,工艺简单。集成接口电路采用了一种内部限幅的环形振荡器电路,将加速度传感器电容值转换为频率信号,并由计数器完成数字信号输出转换。后期测试结果显示,所设计的集成加速度传感器获得了良好的线性度和稳定性能,仅占用0.23mm2芯片面积,1.2V电源电压下消耗了1.4μW功率,尤其适合于无源RFID传感器标签设计中。     

一种低功耗环形振荡器的噪声分析与设计

介绍了一种采用CSMC 0.153 μm CMOS工艺制作的差分环形振荡器。分析了环形振荡器延时单元的选取和设计原理,以及输入差分对管跨导和负载电阻对环振相位噪声的贡献,得到负载为线性区偏置MOS管时低功耗低相位噪声环振的设计方法。在相位噪声变化较小时,采用电容阵列结构拓宽了环形振荡器频率的调谐范围。测试结果表明,该环形振荡器输出频率范围为513 MHz ~1.8 GHz;在振荡频率为1.57 GHz频偏1 MHz处,相位噪声为-84.11 dBc/Hz,功耗为3.88 mW。     

谐振式微加速度计差频检测电路研究

微机械谐振式加速度计的输出频率信号不易受到环境噪声的干扰,在传输和处理过程中也不易出现误差.针对实验室加工的谐振式微机械加速度传感器,采用静电激励和电容拾振的检测方式,设计了电容拾振检测电路和差频输出电路,实现了谐振式加速度计的微弱差频信号检测.利用精密分度盘对该加速度传感器进行了性能测试,实验室测试灵敏度为25.7 Hz/g,达到了设计要求.     

用两个晶振的频率差产生矩形波

图１所示的电路是用两个晶振频率差产生矩形波输出,此电路不需要计数器／分频器、只用两块集成电路。 图１中的ＮＡＮＤ门ＩＣ１构成两个晶体振荡器和一个混频器,混频器输出频率为ｆ１－ｆ２,是两个振荡器的频率差。信号缓冲后到包络检波器,抑制掉所有ＨＦ分量,给出差频输出脉冲。 用图中所示的元件,其检波器带宽高达１００ＫＨｚ（一个晶振频率为３ＭＨｚ）。用两个晶振的频率差产生矩形波     

一种用于CMOS图像传感器的锁相环设计

设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环(CPPLL)电路.基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成.系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求.在输入参考频率为5 MHz时,压控振荡器(VOC)输出频率范围为40～217 MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5 mW,环路带宽为567 kHz,相位裕度为57°,相位噪声为一105 dBc/Hz@1 MHz.     

A new approach to evaluation of hot-carrier lifetime of ringoscillator (RO)

The paper presents a novel experimental method to evaluate AC hot-carrier lifetime of a ring oscillator (RO). By using a series of different stages of ring oscillators (DSROs), the new method allows one to maintain a constant frequency (f₀) and obtain a closer value between pulse-to-pulse voltage (V_p-p) and bias condition throughout the RO lifetime testing. These two achievements eliminate the innate flaws in conventional RO hot-carrier test method. Hence, a more reliable AC lifetime of RO is expected     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

A ring oscillator based frequency synthesizer without using frequency divider

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.     

0.1 THz鳍线单平衡式基波混频电路研究

研究了一种基于石英基片的0.1 THz频段的鳍线单平衡混频电路,混频电路的射频和本振信号分别从WR10标准波导端口通过波导单面鳍线微带过渡和波导微带探针过渡输入,中频信号通过本振中频双工器输出。这是一种新型的混频电路形式,与传统的W波段混频器相比,混频电路可以省略一个复杂的W波段滤波器,具有电路设计简单、安装方便的特点。该电路使用两只肖特基二极管通过倒装焊工艺粘结在厚度为75 m的石英基片上,石英基片相对传统基板,可以极大提高电路加工精度。在固定50 MHz中频信号时,射频90~110 GHz范围内,0.1 THz混频器单边带变频损耗小于9 dB。     

An LO architecture with novel wide locking range,quadrature output RILFDs and ILROs for cognitive radio applications

In this paper, a wide locking range, quadrature output ring type injection locked frequency divider (ILFD) is presented for division ratios of 3 and 4. This ILFD proposes a novel injection scheme that shapes the injection signal to a proper form and provides a convenient situation for divider locking. Furthermore, two new wide locking range, low power consumption, injection locked ring oscillators (ILROs) are proposed for quadrature generation in local oscillator architectures. A novel cognitive radio quadrature local oscillator (LO) architecture is presented by utilizing the proposed ILFDs and ILROs to verify the effectiveness of the proposed circuits. Moreover, a new technique is implemented on the LO architecture to widen the frequency range without consuming any extra power. Because of using a single LC tank, this architecture is very compact. Also, it has the benefit of low power consumption and low output phase noise.     

MOS oscillators with multi-decade tuning range and gigahertzmaximum speed

The author studies the realization of fully integrated MOS oscillators with multidecade tuning range and top speed exceeding 1 GHz. This fast operation requires the use of submicrometer fabrication technology. To overcome the analog circuit limitations of the latter, the design of the oscillator is simplified and, in turn, highly redundant digital and analog control capability is provided. A brief review of possible oscillator structures is given and it is found that the best approach for high-speed, wide-range specifications is the relaxation network of the constant-current charge type. Circuit techniques are presented to increase the speed of the latter, based on active use of parasitics and simplified feedback networks. NMOS and CMOS implementations are discussed and compared. The design and performance of an experimental submicrometer NMOS oscillator is presented. This device covers the 100-kHz-to-1-GHz frequency range and has a robust structure     

Linewidth measurements and phase locking of Josephson oscillatorsusing RSFQ circuits

We present a technique for linewidth measurement and phase-locking of Josephson oscillators using digital rapid single-flux-quantum (RSFQ) circuits. The oscillator consists of a resistively shunted 6 μm×6 μm Nb/AlO_x/Nb Josephson tunnel junction that is integrated with RSFQ input and output circuits. A cascade of RSFQ T flip-flops is used to directly monitor the output of the Josephson oscillator. Spectral characteristics have been measured directly for oscillator frequencies ranging from 10-50 GHz. The linewidth can be reduced by over 100 times by phase-locking the oscillator to an RSFQ pulse train generated by an external sinusoidal signal. These Josephson oscillators can be used as on-chip stable high frequency clocks for RSFQ circuits     

Ring oscillators for CMOS process tuning and variability control

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.