基于多值逻辑方法的二值神经元MOS电路设计技术

提出一种通过引入多值求和信号指导设计二值神经元MOS电路的方法.对每个神经元MOS管的逻辑功能均采用传输开关运算予以表示.在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路.采用所提出的方法综合得到的电路结构十分简单,而且很容易确定各耦合电容之间的取值比例.设计结果同时表明,利用浮栅电压信号易于实现求和的优点,通过引人求和辅助变量可显著简化对电路的综合过程.采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性.     

基于多值逻辑方法的二值神经元MOS电路设计技术

提出一种通过引入多值求和信号指导设计二值神经元MOS电路的方法.对每个神经元MOS管的逻辑功能均采用传输开关运算予以表示.在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路.采用所提出的方法综合得到的电路结构十分简单,而且很容易确定各耦合电容之间的取值比例.设计结果同时表明,利用浮栅电压信号易于实现求和的优点,通过引人求和辅助变量可显著简化对电路的综合过程.采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性.     

采用vMOS管的多值计数器设计

通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。     

新型浮栅MOS单管动态比较器设计

提出一种新型浮栅MOS单管动态比较器的电路结构。以浮栅MOS单管为核心,根据浮栅电荷的保持特性,在时钟控制下,两个电压分时地输入浮栅MOS管从而引起浮栅电位变化,相对变化后的浮栅电位决定着比较管的再通断,使预充电的输出电容与源极电容重新分配电荷,通过输出电容上电压是否发生变化来反映比较结果。单管比较避免差分对管由于工艺偏差所引起的输入失调问题,而且以浮栅偏置抵消MOS管的阈值。采用charted0.35μmCMOS工艺设计电路,面积约为0.003mm2,经前、后仿真和流片测试,结果表明,电路功能正确。并且在3.3V电源电压下、比较时间为0.4μs时,平均功耗为2.8mW。     

新型高精度低功耗电荷传输型匹配单元电路

提出了一种新型电荷传输型电路.电路由MOS管及电容组成,在计算相关量的匹配度时,先计算出相关量的差值,然后将此差值放大,使电路的计算精度提高.采用电荷传输型电路的方式,大大降低了电路的功耗.同时,此电路还具有MOS管阈值偏差自动修正功能,最大限度降低了制造工艺带来的误差.1.5μm双层多晶硅双层铝布线标准CMOS工艺所投样片的测试结果表明,工作频率为50Hz时,功耗仅为12μW.     

新型高精度低功耗电荷传输型匹配单元电路

提出了一种新型电荷传输型电路.电路由MOS管及电容组成,在计算相关量的匹配度时,先计算出相关量的差值,然后将此差值放大,使电路的计算精度提高.采用电荷传输型电路的方式,大大降低了电路的功耗.同时,此电路还具有MOS管阈值偏差自动修正功能,最大限度降低了制造工艺带来的误差.1.5μm双层多晶硅双层铝布线标准CMOS工艺所投样片的测试结果表明,工作频率为50Hz时,功耗仅为12μW.     

64K 静态RAM松下半导体实验室

本文介绍应用双层多晶硅和NMOS/CMOS工艺设计具有典型存取时间为80ns的全静态RAM。该存储器工作和保持方式中功耗分别为300mw和75mw。 该RAM采用了具有N~+掺杂多晶硅栅的N型和P型MOS晶体管的N阱CMOS工艺。通过两步扩散工艺,避免了在形成源漏区的硼离子注入工序中硼掺杂到P型晶体管的硅栅中去,其结果避免了硼穿透400(?)(?)的薄栅氧化层引起P型晶体管的阈值电压漂移的问题。存储单元是在P型衬底上用NMOS工艺制作。外围电路,例如行和列译码器,输入/输出电路及读出放大器等由N阱CMOS形成。     

三值双传输管电路的通用综合方法

提出采用双传管逻辑设计三值电路的方法,对每个MOS管的逻辑功能均采用传输运算予以表示以实现有效综合.建立了三值双传输管电路的反演法则和对偶法则.新提出的三值双传输管逻辑电路具有完全基于标准CMOS工艺,无需对MOS管作任何阈值调整,结构简单、规则,输入信号负载对称性好,逻辑摆幅完整以及无直流功耗等特点.采用TSMC 0.25μm工艺参数和最高电压为3V的HSPICE模拟结果验证了所提出综合方法的正确性.     

三值双传输管电路的通用综合方法

提出采用双传管逻辑设计三值电路的方法,对每个MOS管的逻辑功能均采用传输运算予以表示以实现有效综合.建立了三值双传输管电路的反演法则和对偶法则.新提出的三值双传输管逻辑电路具有完全基于标准CMOS工艺,无需对MOS管作任何阈值调整,结构简单、规则,输入信号负载对称性好,逻辑摆幅完整以及无直流功耗等特点.采用TSMC 0.25μm工艺参数和最高电压为3V的HSPICE模拟结果验证了所提出综合方法的正确性.     

一种新型高线性度MOS采样开关

提出了一种提高MOS采样开关线性度的新方法。通过采用电阻分压电路实现一个处于线性工作状态的“复制”MOS管,使其与采样MOS管具有相同的阈值电压。较之传统栅压自举开关,此新型MOS采样开关能够消除由于阈值电压随输入信号变化所产生的非线性。基于Char-tered 0.35μm标准CMOS工艺设计的新型采样开关,在输入信号为30 MHz正弦波,峰-峰值为1V,采样时钟频率为80 MHz时,无杂散动态范围达到了110 dB,较之自举采样开关提高了12 dB左右;同时,导通电阻的变化减小了90%。     

Neuron MOS binary-logic integrated circuits. I. Design fundamentalsand soft-hardware-logic circuit implementation

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor (νMOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage νMOS inverters. One of the most striking features of νMOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified     

Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors

In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The circuits are designed using two FGMOS basic-cells, each one formed by three floating-gate transistors with common source. The first basic cell is connected in voltage mode, while the second one is connected in current-mode configuration in order to implement voltage and current-mode circuits, respectively. Using the basic FGMOS cells, voltage and current squarers, four-quadrant multipliers and a current square rooter are designed. Mismatches and distortion analysis for the proposed circuits have been elaborated. The most important advantages are, rail-to-rail dynamic input range, low distortion and ability for either differential or single-ended input signals. Simulation results demonstrate the feasibility and the accuracy of the circuits.     

A neuron-MOS neural network using self-learning-compatible synapsecircuits

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (υMOS) as a key circuit element. A υMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based on the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept υMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V_DD power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of υMOS neural networks. The basic operation of the synapse cell and a υMOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process     

A high-performance BICMOS Technology with double-polysilicon self-aligned bipolar devices

A high-performance BICMOS technology is described which incorporates 12-GHz double-polysilicon self-aligned bipolar, fully salicided CMOS devices and 1-µm features. This process is applied to a new BICMOS gate design, called transistor feedback logic (TFL), to fabricate a divide-by-16 frequency divider with a maximum operating frequency of 364 MHz. Availability of uncompromised MOS and bipolar transistors allows a free mix of pure CMOS, pure bipolar, or BICMOS gates on the same chip.     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

NORA: a racefree dynamic CMOS technique for pipelined logic structures

Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.     

Neuron MOS binary-logic integrated circuits. II. Simplifyingtechniques of circuit configuration and their practicalapplications

For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The νMOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices

This paper proposes an analog CMOS circuit that implements a central pattern generator (CPG) for locomotion control in a quadruped walking robot. Our circuit is based on an affine transformation of a reaction-diffusion cellular neural network (CNN), and uses differential pairs with multiple-input floating-gate (MIFG) MOS transistors to implement both the nonlinearity and summation of CNN cells. As a result, the circuit operates in voltage mode, and thus it is expected to reduce power consumption. Due to good matching accuracy of devices, the circuit generates stable rhythmic patterns for robot locomotion control. From experimental results on fabricated chip using a standard CMOS 1.5-/spl mu/m process, we show that the chip yields the desired results; i.e., stable rhythmic pattern generation and low power consumption.     

Novel pseudo-exponential circuits

In this paper, two voltage-mode circuits that implement the pseudo-exponential function using controllable gain blocks are presented. The gain block of the proposed circuits each utilize a current conveyor and an operational amplifier in a novel manner. They offer the advantages that they are precise, easily implemented in integrated circuit (IC) form and can employ a bank of switched resistors, MOS transistors in triode or transconductors to change their gain according to a control parameter /spl chi/ that is determined by a ratio of resistances. Experimental results using discrete IC components confirm the theory and show the circuits having an output range of approximately 22 dB, with an error of less than 1 dB for x greater than -0.55 and less than 0.63.