Modeling and characterization of gate oxide reliability

A technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented. Using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. This modeling procedure is applicable to both wafer-level and long-term reliability tests. Process improvements including defect gettering and alternative dielectrics such as chemical-vapor-deposited oxides are evaluated in the format of defect density as a function of effective oxide thinning     

Modeling manufacturing yield and reliability

In this paper, we introduce the concept of reliability defect, present the time-dependent defect growth model during operations based on a defect-related gate oxide breakdown mechanism, and build the yield-reliability relation model. Discussions presented here can also be applicable to other device failures when different physics-of-failure mechanisms are found. Through the relation model, it is possible to find a minimum level of latent defect screening to assure the required level of reliability and predict reliability for new products when it is combined with a yield prediction model     

A relation model of gate oxide yield and reliability

The relationship between yield and reliability is obviously important for predicting and improving reliability during the early production stage, especially for new technologies. Previous research developed models to relate yield and reliability when reliability is defined as the probability of a device having no reliability defects. This definition of reliability is not a function of mission time and thus is not consistent with reliability estimated from the time-to-first-failure data which is commonly used. In this paper, we present a simple model to tie oxide yield to time-dependent reliability by combining the oxide time to breakdown model with a defect size distribution. We show that existing models become special cases when a single mission time is considered. As the proposed reliability function has a decreasing failure rate, the result is useful for a manufacturer seeking to find an optimal burn-in policy for burn-in temperature, burn-in voltage, and burn-in time.     

Defining the safe operating area for HBTs with an InGaP emitter across temperature and current density

Statistical methods are applied for determination of the safe operating area (SOA) of HBTs across temperature and current density in terms of the FIT rate. Black’s equation is employed to predict the MTTF and likelihood methods are used to obtain the parameter estimates. Confidence intervals on the FIT rate are determined by two different methods and good agreement between the two techniques is observed. The final product of this analysis is a reliability “map” that allows the engineer to make trade-offs between current density and junction temperature when designing to a given reliability level.     

Relating integrated circuit yield and time-dependent reliability for various defect density distributions

The issue of developing a model to estimate field reliability from process yield has received a growing interest in recent years. Thus far, only Poisson and negative binomial relationships have been obtained, assuming that the number of yield defects is independent of the number of reliability defects in a device. In this paper, we derived explicit yield-reliability relationships for various defect density, such as Erlang, uniform, and triangle distributions, using a multinomial distribution to consider a correlation between the number of yield defects, and the number of reliability defects. The proposed model has advantages over previous models for any defect density distribution to determine the optimal burn-in time.     

Projecting gate oxide reliability and optimizing reliabilityscreens

The effect of time-dependent stress voltage and temperature on the reliability of thin SiO₂ films is incorporated in a quantitative defect-induced breakdown model. Based on this model, design curves which can be used along with a breakdown voltage distribution for an oxide technology to determine optimal burn-in conditions are presented. The tradeoff between improved reliability and lower burn-in yield for different gate oxide technologies can also be examined quantitatively using the model     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

Reliability versus yield and die location in advanced VLSI

The results of multiple correlations between reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures.The model that reliability defect density is proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.     

A new reliability prediction model for telecommunication hardware

An analysis of measured field failure rates of printed circuit boards has been performed. The “part count” method currently used for reliability predictions was evaluated. A new model for electronic reliability prediction has been proposed. It uses statistics from board and system tests performed at the production plant and the number of conductive layers on the board. The report shows that there is a correlation between production test statistics and field performance, for high-volume boards. The proposed model shows that a high production test yield indicates high field reliability. This means that if actual production test results are poor, actions can be taken to improve reliability before numerous boards are delivered to customers.     

The physics of determining chip reliability

We have indicated the necessity for using statistical models to determine the reliability of deep-submicron MOSFETs. We have presented a methodology by which the reliability can be determined from short-time tests if the defect generation statistics are linked to variations in defect activation energies. We have shown that enhanced latent failures follow from our model for deep-submicron MOSFETs. Therefore, more stringent reliability standards are required, which can be validated by the use of short-time tests. Our model provides the means to calculate these novel reliability demands quantitatively     

Yield and reliability issues in nanoelectronic technologies

Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that follow the rates predicted in Moore’s law. The tradeoffs in area, speed and power, allowed by theCmos technology, and its capacity to integrate analog, digital and mixed components, are key features to its dissemination in the telecommunications field. In fact, the progress of theCmos technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. As integrated circuits evolve, they approach some limits that make further improvements more difficult and even unpredictable. With deep-submicron structures, the yield of manufacturing processes is one of the main challenges of the semiconductor industry, with negative impacts on time-to-market and profitability. With reduced voltages and increased speed and density, the reliability of deep-submicron circuits is another concern for designers, since noise immunity is reduced and thermal noise effects show-up. In this paper we present an overview of the issues related with the scaling of integrated circuits into nanometer technologies, detailing the yield and reliability problems. We present the state of the art in proposed solutions and alternatives that can improve the chances of a large utilization of these nanotechnologies.     

Determination of safe reliability region over temperature and current density for through wafer vias

Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10 years at T = 125 °C and J = 0.25 × 10⁶ A/cm². The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a “reliability map” for designers allowing trade-offs between temperature current to be made when designing for high reliability.     

Methodology for predicting off-state reliability in GaN power transistors

Results of a lifetest across temperature and drain voltage on off-state high power GaN FET test structures are presented. The times to failure (t_f) are fitted to a combination of the Arrhenius model (ln(t_f) ∼ inverse temperature) and the linear field model (ln(t_f) ∼ drain voltage). The estimated activation energy (E_a) is 2.1 eV and the estimated linear field parameter (γ) is 0.03 V⁻¹. Reliability parameters estimated from the test structure data are used to predict the FIT rate for a product level FET using linear scaling of the gate width. Further, the effect of a burn-in and a transient voltage under a duty cycle on the FIT rate are modeled. The FIT rate of the product level FET is larger than that of the test structure. The burn-in and transient voltage similarly reduce the reliability. Contour plots are given that allow trade-offs between these factors in order to meet reliability requirements.     

Modeling gallium arsenide heterojunction bipolar transistor ledge variations for insight into device reliability

It is widely known that under normal bias conditions, GaAs heterojunction bipolar transistor (HBT) device degradation proceeds by a gradual buildup of defects in the base and base–emitter junction depletion regions. The buildup of these defects is associated with a solid-state phenomenon known as recombination enhanced defect reaction, which is the formation and migration of defects associated with nonradiative electron–hole recombination events. These defects are often associated with midgap traps, which serve as additional recombination centers for electron–hole pairs. The resulting increased recombination current is an additional base leakage current, which reduces current gain. By extension, a high electron–hole recombination density in a region with an initially high defect density––such as an unpassivated or poorly passivated base surface––will lead to quick device degradation.This paper reports the modeling of the effects of various different extrinsic base passivation ledge parameters––material composition, thickness, width, and spacing from ledge to base contact––to determine the microscopic effects these parameters have on electron–hole recombination density. Through this we can qualitatively predict the effects these parameters will have on HBT reliability.     

缺陷引起的可靠性和成品率关系研究

为了在满足最低可靠性要求的同时尽量提升Ic的成品率,基于缺陷的泊松分布模型及负二项分布模型研究了由缺陷引起的Ic可靠性和成品率这两者之间的关系,并分别建立了相应的成品率一早期可靠性关系模型。基于成品率一可靠性模型,针对氧化层缺陷模型,采用模拟运算的方法,得到了随时间变化的成品率一可靠性关系模型。模型表明,在满足最低可靠性要求的同时,合理设计老化实验参数,可以最大限度地提高成品率,降低Ic制造成本。最后根据这一模型对Ic老化筛选实验的参数选择提出了优化的建议。     

MOS VLSI reliability and yield trends

The yield and reliability capability of an MOS technology are shown to be the product of at least six different technological trends; namely those towards: 1) more complex device structures, 2) scaled down feature sizes, 3) increased wafer sizes, 4) factory automation, 5) increased die size and package lead counts, and 6) increasingly sophisticated computer-aided design tools. The capabilities of a specific technology are a function of the equipment and processes by which it is manufactured and these are often the rate-limiting factors for evolution to the next generation of technology. However, because of the impact of scaling trends on MOS IC failure mechanisms, reliability concerns are starting to dominate the rate of technology change. This is evidenced, even at the present, by the fact that technology decisions must be made by trading off one reliability failure mechanism against another. For example, the high storage charge density needed to provide strong signals for alpha-particle-induced soft error immunity, produces high electric fields and oxide breakdown problems in thin-oxide MOS storage capacitors. Failure distribution for both failure mechanisms are shown to be exponentially dependent (in an inverse manner) on the scale factor for oxide thickness. Hot-electron degradation is also exponentially dependent on the scale factor for channel length. Metal and contact electromigration lifetimes can be reduced by the seventh and nineth powers of scale factor, respectively. The implications are that the dominant reliability mechanisms may change in the future, and that wearout will start to impinge on reliability life.     

The effect of hot electron current density on nMOSFET reliability

In this paper, we consider the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique. We confirm that there is a dependence of oxide degradation upon the current density during SHE injection (as previously observed by ourselves and others). In order to explain this effect, the detrapping of previously trapped electrons must be taken into account A new theoretical model is presented which accounts for the main features of the phenomenon. We consider the technologically important low field case (< 2MVcm⁻¹) for a range current densities (from 0.05 to 2 mAcm⁻²) and injected charge densities up to 10 C/cm². The device lifetime for these different conditions is calculated and shown to be also a function of the current density. It is clear that in order to calculate the lifetime during normal operation from accelerated testing, the precise hot electron injection current density must be known, furthermore it must be demonstrated that the same degradation mechanisms hold at very high fields and/or current densities. This result has profound implications for device reliability predictions made using accelerated hot electron measurements and calls into question lifetime predictions made where the effect is not taken into account.     

Quality and mechanical reliability assessment of wafer-bonded micromechanical components

Strength tests and fracture mechanics models for Silicon wafer-bonded components are presented which can be applied during the development of bonding technologies, for the yield improvement and failure analysis] as well as for the reliability assessment of micromechanical sensors and actuators. Special attention is given to the influences of atomic bonding strength, the interface voids and the notches caused by etching steps prior to bonding on the fracture limit. If wafer-bonded interfaces are exposed to a mechanical loading for an extended time, e.g. in the order of months or years, stress corrosion effects decrease the bonding strength. As a consequence, stressed sensors and actuators fabricated by wafer bonding can suddenly fail during application after a load-dependent lifetime. Based on an appropriate fracture mechanics model, the time-to-failure data could be theoretically predicted.     

Reliability estimation of BGA and CSP assemblies using degradation law model and technological parameters deviations

Very low failure rates, down to 10 FITs (one FIT is equivalent to one failure per 10⁹ h × component), are now currently expected for electronics devices. To assess this challenge even for complex assemblies, process control, design and technological solutions must be optimised to guarantee almost no defect during the operating life. Reliability evaluation must also evolve from classical accelerated tests, towards the use of more sophisticated laws based on physics of failure and process parameters. We present results from BGA and CSP thermocycling measurements where expected cumulative failure distributions have been modelled using computed degradation law and process dispersion data.Starting points are:

• An already validated evolution law models the observed degradations on test samples of two different assembly technologies.

• Numerous physical simulations of technological attributes deviations, using process data are performed.

• Statistical computations using the previous results lead to a theoretical lifetime distribution under various stress conditions.

• The extrapolated results related to reliability functions are compared to experimental tests.