一种低复杂度的MIMO预处理球形译码算法

提出了一种新的低复杂度MIMO预处理球形译码算法.球形译码算法是MIMO译码方案达到最大似然性能的低复杂度译码算法,但当信噪比较低或调制阶数较高时,该算法的复杂度仍然很大,甚至接近穷尽搜索方法的复杂度.本文利用迫零译码的初始估值作为软信息,对信道矩阵各列进行重排列,从而改变解向量中各维信号的求解顺序,因此大大减少了低信噪比或较高调制阶数的球形译码计算复杂度.仿真结果表明,当Eb/No为0～3时,16QAM调制方式下的V-BLAST译码复杂度减少了近1/3.     

一种低复杂度空间调制球形译码检测算法

现有的空间调制系统球形译码（Sphere-Decoding,SD）检测算法虽然能够较大地降低最大似然（Maximum-Likelihood,ML）检测算法的计算复杂度,但由于其更新半径比较松散、收敛较慢,计算复杂度降低的水平仍十分有限,尤其是在高阶调制系统下.针对上述问题,采用统计分布的思想对现有算法更新半径中的冗余项进行估计,提出了两种改进的球形译码检测算法.理论分析与仿真结果表明,改进算法在达到最优检测性能的同时,极大地降低了传统球形译码的计算复杂度,具有较好的理论和实际应用意义.     

极化码序列连续删除译码算法的改进设计

极化码连续删除译码算法性能和传统的LDPC码存在一定差距。序列连续删除算法(SCL)的提出极大地改善译码性能,是极化码推向实际应用中的重要一步。但是该算法复杂度较高,延迟大。改进的序列连续删除(SCL)译码算法是基于改善极化码码长受限的情况,文中描述SCL算法是通过码树上的搜索序列路径来表示译码过程。改进的算法通过减少译码算法在码树上的序列路径来降低时间和空间复杂度。通过仿真表明,改进的算法有效地降低了译码的复杂度同时在性能上也接近最大似然(ML)译码算法。     

基于分段循环冗余校验的极化码自适应连续取消列表译码算法

针对极化码连续取消列表(SCL)译码算法为获取较好性能而采用较多的保留路径数,导致译码复杂度较高的缺点,自适应SCL译码算法虽然在高信噪比下降低了一定的计算量,却带来了较高的译码延时。根据极化码的顺序译码结构,该文提出了一种分段循环冗余校验(CRC)与自适应选择保留路径数量相结合的SCL译码算法。仿真结果表明,与传统CRC辅助SCL译码算法、自适应SCL译码算法相比,该算法在码率R=0.5时,低信噪比下(–1 dB)复杂度降低了约21.6%,在高信噪比下(3 dB)复杂度降低了约64%,同时获得较好的译码性能。     

MIMO系统中k-best球形译码算法研究

通过对广度优先策略中有恒定复杂度的层排序k-best球译码算法进行分析,提出一种每节点保留可变扩展节点的层排序k-best球形译码算法(k-best SDA Ⅱ),在64QAM调制及每层保留8节点的实数SDA模型下,通过仿真的方法得出了保留恒定扩展节点的k-best SDA当每节点保留扩展节点数大于等于2时,性能基本不变(k-best SDA Ⅰ);而改进的k-best SDA Ⅱ则对k-best SDA Ⅰ在性能与复杂度上作了比较好的折中,前者计算复杂度大约减少了28%,而性能的损失基本可以忽略.     

LTE-A系统一种降低复杂度的软球形检测算法

软球形译码算法虽然能接近ML(最大似然)算法的误码性能,但其计算复杂度很高。文章提出了一种降低计算复杂度的SSD(软球形译码)算法,该算法在QR(正交三角)分解算法的反向迭代上三角矩阵R中引入减弱噪声部分以缩小初始搜索半径,然后利用最小距离准则对搜索树进行有效地删减,缩小树搜索空间。MATLAB仿真结果表明,该算法在获得接近传统SSD性能的条件下,能够很大程度地降低系统的计算复杂度。     

连续衰落信道下适用于酉空时调制的最大似然多符号差分检测算法

为酉空时调制系统设计的多符号差分球形译码(MSDSD)能以较低复杂度获得最大似然(ML)检测性能。但是,该算法基于准静态信道假设,当将它用于快衰落信道时会出现严重的误码平层现象。本文基于连续衰落信道假设,推导了一种ML度量的递推形式,并将其嵌入自动球形译码算法中,得到了的多符号差分自动球形译码(MSDASD)算法。该算法适用于一般酉空时星座,克服了MSDSD的误码平层现象,可达到ML检测的性能,其平均复杂度在大多数情况下低于相同假设下的判决反馈检测算法。     

MIMO低复杂度空时分组码译码算法研究

研究了空时分组码译码算法的运算简化问题,提出了一种基于最大似然检测的改进空时分组码低复杂度译码算法,并进行了译码性能仿真和运算复杂度对比。本丈提出的改进方法,能够在不影响系统译码性能的基础上,有效地降低空时分组码的译码复杂度,且译码复杂度受调制星座图大小的影响很小。     

基于修正扩展信道矩阵的球形解码算法

球形解码算法是多输入多输出(MIMO)系统一种性能较好的信号检测算法,只是其计算复杂度较高,为此,有学者提出运用最小均方误差(MMSE)和压缩系数控制的初始半径来降低复杂度,然而对于16QAM调制的情形,该算法虽能降低复杂度却也损失了部分误码率。针对这一问题,文章提出一种基于修正扩展信道矩阵的球形解码算法,仿真结果表明,改进的算法在16QAM调制时不仅可以改善信号的误码率,而且基本不增加算法的计算复杂度。     

Turbo乘积码译码算法的简化

Chase算法是Turbo乘积码(TPC)软判决译码中常采用的算法之一。分析了传统Chase算法中寻找竞争码字对译码复杂度的影响,在此基础上提出了两种新的简化译码算法,省去了寻找竞争码字的过程。仿真结果表明,简化算法在基本保持传统Chase算法译码性能的基础上,降低了译码复杂度,提高了译码速度。     

Decoding the Golden Code: A VLSI Design

The recently proposed Golden code is an optimal space-time block code for 2$,times,$ 2 multiple-input–multiple-output (MIMO) systems. The aim of this work is the design of a VLSI decoder for a MIMO system coded with the Golden code. The architecture is based on a rearrangement of the sphere decoding algorithm that achieves maximum-likelihood (ML) decoding performance. Compared to other approaches, the proposed solution exhibits an inherent flexibility in terms of QAM modulation size and this makes our architecture particularly suitable for adaptive modulation schemes. Relying on the flexibility of this approach two different architectures are proposed: a parametric one able to achieve high decoding throughputs ($>$ 165 Mb/s) while keeping low overall decoder complexity (45 KGates), a flexible implementation able to dynamically adapt to the modulation scheme (4-,16-,64-QAM) retaining the low complexity and high throughput features.      

一种M-QAM软判决解映射的简化算法研究

提出了一种适用于所有M-QAM软判决解映射的简化算法,并将其扩展到不对称的二维QAM解映射中,如DTMB中的32-QAM.并以32-QAM为例,用计算机仿真比较了不同算法的编码系统误码率和解码时间等性能.结果表明,在'降低M-QAM软判决解映射的判决复杂度时,该简化算法没有损失信噪比,性能良好,适用于DTMB系统.     

结合6-QAM和双层LDPC码的编码调制研究

针对阶数为3×2p的非标准调制与纠错编码难以匹配的问题,提出了一种面向6阶正交幅度调制（QAM）的双层编码调制传输方案。在发送端,采用有限域GF(2)低密度奇偶校验（LDPC）码与GF(3) LDPC码进行分层编码,并将两种编码码字映射为6进制码字后进行6-QAM调制;在接收端,根据GF(2) LDPC码和GF(3) LDPC码的译码顺序,设计了两种双层迭代译码方法。仿真结果表明,在加性高斯白噪声（AWGN）信道下,执行一次整体迭代译码时,先执行GF(3) LDPC码译码的6-QAM分层编码调制方案比先执行GF(2) LDPC码译码的方案获得了更优的误符号率（SER）性能;随着迭代次数增加,纠错性能可获得进一步改善。比较6-QAM与6阶相移键控（6-PSK）调制,若先执行GF(3) LDPC码译码,当SER为10-5时,6-QAM结合双层LDPC码的传输方案在AWGN信道下可获得约1.3dB的增益。      

Algorithm and implementation of the K-best sphere decoding for MIMO detection

K-best Schnorr-Euchner (KSE) decoding algorithm is proposed in this paper to approach near-maximum-likelihood (ML) performance for multiple-input-multiple-output (MIMO) detection. As a low complexity MIMO decoding algorithm, the KSE is shown to be suitable for very large scale integration (VLSI) implementations and be capable of supporting soft outputs. Modified KSE (MKSE) decoding algorithm is further proposed to improve the performance of the soft-output KSE with minor modifications. Moreover, a VLSI architecture is proposed for both algorithms. There are several low complexity and low-power features incorporated in the proposed algorithms and the VLSI architecture. The proposed hard-output KSE decoder and the soft-output MKSE decoder is implemented for 4/spl times/4 16-quadrature amplitude modulation (QAM) MIMO detection in a 0.35-/spl mu/m and a 0.13-/spl mu/m CMOS technology, respectively. The implemented hard-output KSE chip core is 5.76 mm/sup 2/ with 91 K gates. The KSE decoding throughput is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The implemented soft-output MKSE chip can achieve a decoding throughput of more than 100 Mb/s with a 0.56 mm/sup 2/ core area and 97 K gates. The implementation results show that it is feasible to achieve near-ML performance and high detection throughput for a 4/spl times/4 16-QAM MIMO system using the proposed algorithms and the VLSI architecture with reasonable complexity.     

Reduced complexity in-phase/quadrature-phase M-QAM turbo equalization using iterative channel estimation

A reduced complexity trellis-based turbo equalizer known as the in-phase (I)/quadrature-phase (Q) turbo equalizer (TEQ-IQ) invoking iterative channel impulse response (CIR) estimation is proposed. The underlying principle of TEQ-IQ is based on equalizing the I and Q component of the transmitted signal independently. This requires the equalization of a reduced set of separate I and Q signal components in comparison to all of the possible I/Q phasor combinations considered by the conventional trellis-based equalizer. It was observed that the TEQ-IQ operating in conjunction with iterative CIR estimation was capable of achieving the same performance as the full-complexity conventional turbo equalizer (TEQ-CT) benefiting from perfect CIR information for both 4- and 16-quadrature amplitude modulation (QAM) transmissions, while attaining a complexity reduction factor of 1.1 and 12.2, respectively. For 64-QAM, the TEQ-CT receiver was too complex to be investigated by simulation. However, by assuming that only two turbo equalization iterations were required, which is the lowest possible number of iterations, the complexity of the TEQ-IQ was estimated to be a factor of 51.5 lower than that of the TEQ-CT. Furthermore, at BER = 10/sup -3/ the performance of the TEQ-IQ 64-QAM receiver using iterative CIR estimation was only 1.5 dB away from the associated decoding performance curve of the nondispersive Gaussian channel.     

基于无率纠错码和高阶QAM调制的收端速率自适应方案

现有的自适应解调方案中调制阶数最高仅限于16,且方案分析和设计中没有考虑信道编码的译码环节.本文研究适用于高阶QAM的自适应解调算法,并结合无率纠错码提出一种收端速率自适应方案.接收端有多种解调模式,每种解调模式删除一个符号中不同数量的、似然比绝对值最低的几个比特,以提高解调比特的可靠度和平均互信息.从互信息分析的角度,得到在满足要求的译码误码性能时,译码所需要的码字长度的理论结果,进一步给出在译码复杂度约束条件下解调模式的选择方案.以256-QAM调制星座和Raptor码为例对方案进行了仿真,验证了理论分析的正确性和方案的有效性.     

Parallel High Throughput Soft-Output Sphere Decoding Algorithm

Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. To speed up the computation, we propose a scheme with multiple fixed complexity sphere decoders to construct a parallel soft-output fixed complexity sphere decoder (PFSD). The proposed decoder is highly parallel and has performance comparable to soft-output list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate that the PFSD algorithm can increase the throughput and reduce bit error rate of a soft-output solution in a 4 × 4 16-QAM system, and has superior performance compared to other soft decoders with comparable throughput and computation complexity. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can achieve up to 75 Mbps throughput for 4 × 4 64-QAM configuration at 100MHz with low control overhead.     

Multi-resolution 64-DAPSK modulation in a hierarchical COFDMtransmission system

Two alternative modulation schemes of 64-QAM (quadrature amplitude modulation) and 64-DAPSK (differential amplitude and phase shift keying) with a coherent and incoherent demodulation have been proposed for digital terrestrial video broadcasting (DTVB) in combination with the coded orthogonal frequency division multiplexing (COFDM) technique (Schafer 1995, and Engels and Rohling 1995). Additionally, a hierarchical transmission system based on a multi-resolution (MR) 64-QAM is described in Engels and Rohling which extends the service area of a TV programme in decoding a stepwise reduced data rate with increasing transmitter distance (graceful degradation). This procedure corresponds to a decreasing picture quality. In this paper MR concepts for the 64-DAPSK are developed. A performance comparison between the hierarchical transmission systems (MR-64-QAM/OFDM and MR-64-DAPSK/OFDM) is described for the uncoded and coded case     

A 74.8 mW Soft-Output Detector IC for 8 8 Spatial-Multiplexing MIMO Communications

In this paper, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed chip can support up to 8 $, times ,$8 64-QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2$,times,$ 2 up to 8$,times,$ 8 and modulation order from QPSK to 64-QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input channel decoders and iterative decoding system. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and superior error rate performance, called modified best-first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-dual-heap (quad-DEAP) circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this chip is configured as 4$, times ,$4 64-QAM and 8$, times ,$ 8 64-QAM soft-output MIMO detectors, it achieves average throughputs of 431.8 Mbps and 428.8 Mbps with only 58.2 mW and 74.8 mW respective power consumption and reaches 10$^{-5}$ coded bit error rate (BER) at signal-to-noise ratio (SNR) of 24.2 dB and 22.6 dB, respectively.