一种3D堆叠集成电路中间绑定测试时间优化方案

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.     

3D芯片绑定中测试绑定次序对成本的影响

针对3D SICs（3D Stacked Integrated Circuits,三维堆叠集成电路）在多次绑定影响下的成本估算问题,现有的方法忽略了实际中经常发生的丢弃成本,从而使得理论的测试技术不能很好的应用于实际生产.本文根据绑定中测试的特点,提出了一种协同考虑绑定成功率与丢弃成本的3D SICs理论总成本模型.基于该模型,提出了一种3D SICs最优绑定次序的搜索算法.最后,进一步提出了减少绑定中测试次数的方法,实现了"多次绑定、一次测试",改进了传统绑定中测试"一绑一测"的方式.实验结果表明,本文提出的成本模型更贴近于实际生产现状,最优绑定次序、最优绑定中测试次数可以更加有效指导3D芯片的制造.     

3D TSV测试的挑战和潜在解决方案(英文)

3D硅通孔技术增加电路密度、降低功耗、提高带宽的优势在业内已得到广泛的认可。随着3D TSV技术的迅速发展,对于测试成本的优化就显得尤为突出,现有的测试方法已提出了很多挑战3D TSV技术的解决方案。提出了一种不同的应对3D TSV测试技术挑战的完整的3DTSV测试解决方案,其中某些方面涉及到3D TSV测试的前沿技术,而且也是唯一面向3D TSV测试特定的解决方案。最后,给出了一些采用完整3D TSV测试中其余的挑战。     

基于聚类的异步时钟SoC测试

为进一步减少片上系统(System-on-Chip,SoC)测试耗时、降低测试成本,本文结合异步时钟测试机制,提出一种基于聚类的测试调度方法.该方法利用了SoC各测试的特征以及异步时钟测试的特点,对测试数据进行预处理.在ITC'02基准SoC集上,将本文方法与未采用异步时钟机制以及基于混合整型线性规划模型求解的方法进行对比.结果表明,本文的方法分别能平均减少测试耗时20.39％和5.53％,提升了调度算法的优化效率.并且在功耗约束较强时,最终调度结果与耗时下界仅相差0.9％.     

迎击SoC测试新挑战安捷伦93000单一平台包揽多种测试应用

由于要将多种功能融合在单一芯片,使得SoC芯片设计更为复杂,如何降低测试成本成为开发商的当务之急.对此,安捷伦科技半导体测试事业部推出创新概念的93000单一测试平台,提供缩短测试时间、降低测试成本的理想选择,目前全球已经安装了900多套93000系统.     

基于边沿延时翻转的绑定前硅通孔测试方法

硅通孔（Through-Silicon Via,TSV）在制造过程中发生开路和短路等故障会严重影响3D芯片的可靠性和良率,因此对绑定前的TSV进行故障测试是十分必要的.现有的绑定前TSV测试方法仍存在故障覆盖不完全、面积开销大和测试时间大等问题.为解决这些问题,本文介绍一种基于边沿延时翻转的绑定前TSV测试技术.该方法主要测量物理缺陷导致硅通孔延时的变化量,并将上升沿和下降沿的延时分开测量以便消除二者的相互影响.首先,将上升沿延时变化量转化为对应宽度的脉冲信号;然后,通过脉宽缩减技术测量出该脉冲的宽度;最后,通过触发器的状态提取出测量结果并和无故障TSV参考值进行比较.实验结果表明,本文脉宽缩减测试方法在故障测量范围、面积开销等方面均有明显改善.     

SoC芯片可测试性设计策略分析

微电子器件已经广泛应用于航空航天等多个领域中,发挥着重要作用。随着芯片技术的升级,集成电路不断缩小尺寸,系统级芯片（SoC）已经得到广泛应用,且对于SoC芯片需求量逐渐增多。基于此,文章通过分析SoC芯片结构,进一步研究可测试性设计,以阐述测试性能控制方法,实现性能和效率的优化。在测试中利用芯片功能模块接口和外部端口存在的映射关系,通过锁存器和JTAG进行控制。通过可测试性设计能够缩短测试时间,降低测试成本,支持芯片质量和成本效益的提高。     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

基于TAM分组策略的SoC测试多目标优化设计

在片上系统芯片（System-on-Chip ,SoC）测试优化技术的研究中,测试时间和测试功耗是相互影响相互制约的两个因素。在基于测试访问机制（Test Access Mechanism ,TAM ）分组策略的基础上,以测试时间和测试功耗为目标建立了联合优化模型,运用多目标遗传算法对模型进行求解。以ITC’02标准电路中的p93791电路为实例进行验证,表明此方法能够在测试时间和测试功耗的优化上获得较理想的解,且能提高TAM通道的利用率。     

Synopsys DFT MAX助珠海炬力节省90％测试成本

Synopsys日前宣布珠海炬力已采用其DFT MAX扫描压缩自动化解决方案实现其0．13微米SoC设计，使测试设备相关成本降低90％。DFT MAX通过片上扫描数据压缩。可显著减少高质量制造测试所需的测试时间和测试数据量。     

一种面向应用优化的片上总线调度策略

该文提出了一种面向应用优化的片上总线调度策略。以系统通信事件信息为基础,使用最小任务松弛时间与最小总线空闲时间相结合的调度策略,在优先保证满足任务实时要求的基础上,最大限度利用总线空闲时间,提高调度效率。并提供了可配置的权重参数用于总线时间消耗与片上缓冲区容量之间的设计折衷。在双核SoC平台上实现了本文调度方法,并以最新视频编解码标准H.264/AVC为目标应用,与FP(Fixed Priority),SBA(Slack Based Arbitration),RR(Round Robin)等调度方法进行了性能对比。实验结果表明,=0.5时,较以上3种策略,分别平均可减少16.6％、13.2％与9.7％的总线时间,在实时性能方面,较最接近的SBA方法,未实时完成的任务数量减少了59.4％。额外缓冲区开销随的变化关系表明,在最坏情况下(=0)仅需435字节。     

Low-power multi-core ATPG to target concurrency

A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

Fast algorithms for test optimization of core based 3D SoC

The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.     

复用NoC测试IP芯核测试存取链优化配置

论述了层次型IP芯核不同测试模式之间的约束关系,给出了层次型IP芯核的测试壳结构,提出了一种复用片上网络测试内嵌IP芯核的启发式测试存取链优化配置方法.该方法可有效减小测试数据分组数量和被测芯核的测试时间.使用片上网络测试平台,在测试基准电路集ITC'02中的基准电路p22810上进行了实验验证.     

基于SoC设计的软硬件协同验证技术研究

软硬件协同验证是SoC设计的核心技术。其主要目的是验证系统级芯片软硬件接口的功能和时序,验证系统级芯片软硬件设计的正确性,以及在芯片流片回来前开发应用软件。本文介绍了基于SoC设计的软硬件协同验证方法学原理及其验证流程。然后分析了SoC开发中采用的3种软硬件协同验证方案,ISS方案、CVE方案、FPGA／EMULATOR方案,对其验证速度、时间精度、调试性能、准备工作、价格成本、适用范围等各方面性能做出比较并提出应用建议。     

ATE测试成本优化

多点测试是降低片上系统测试成本的有效手段,目前支持多点测试的ATE(自动测试设备)越来越多。多点测试通过并行测试多个芯片降低了测试成本,但是如何选择多点测试使得测试成本最低,需要综合考虑多方面因素,包括ATE成本、芯片的测试策略等。文中从ATE出发,建立芯片的测试成本模型,通过该模型获得了最佳测试方案。     

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.      

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.